intel/xeon_sp/cpx: Hook up public microcode release

Change-Id: I7e575cb17e2004bd931f4fa1d05f17c4cdca29ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

Documentation/mainboard/ocp/deltalake.md

@@ -24,7 +24,8 @@ Delta Lake server OSF solution requires:
 - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
   is not yet available to the public. It will be made public soon by Intel 
   with redistributable license.
-- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
+- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
+  coreboot.org mirrors this repo and by default the correct binary is included.
 - ME binary: Ignition binary will be made public soon by Intel with
   redistributable license.
 - ACM binaries: only required for CBnT enablement. Available under NDA with Intel.

src/soc/intel/xeon_sp/cpx/Kconfig

@@ -4,7 +4,6 @@ if SOC_INTEL_COOPERLAKE_SP
 
 config SOC_SPECIFIC_OPTIONS
 	def_bool y
-	select MICROCODE_BLOB_NOT_HOOKED_UP
 
 config FSP_HEADER_PATH
 	  string "Location of FSP headers"

src/soc/intel/xeon_sp/cpx/Makefile.inc

@@ -17,4 +17,6 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
 
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-55-0b
+
 endif ## CONFIG_SOC_INTEL_COOPERLAKE_SP