nb/intel/haswell: Implement proper backlight PWM config
Further backport the backlight-PWM handling from Skylake. Beside configuring the PWM frequency in Hz, we also use the PCH's logic for the brightness setting via BLM_PCH_OVERRIDE_ENABLE. Linux would toggle it anyway and that might confuse our ASL code. We assume that the 183Hz value that was set before for Slippy variants was overridden by Linux with the 200Hz VBT value, like it was for the Broadwell Chromebooks. So we set 200Hz for them in the devicetrees. The calculated value for the T440p of 220Hz seems sane and also matches the VBT. Change-Id: I17dfe1a3610d5e2918c617cf5d10896692fdccb3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Nico Huber
Matt DeVillier
parent
8107c81e07
commit
c2e46420cc
|
|
@ -3580,6 +3580,7 @@
|
|||
#define SOUTH_CHICKEN2 0xc2004
|
||||
#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
|
||||
#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
|
||||
#define LPT_PWM_GRANULARITY (1<<5)
|
||||
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
|
||||
|
||||
#define _FDI_RXA_CHICKEN 0xc200c
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@ chip northbridge/intel/haswell
|
|||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM values for eDP
|
||||
register "gpu_cpu_backlight" = "0x00000200"
|
||||
register "gpu_pch_backlight" = "0x04000000"
|
||||
# Set backlight PWM value for eDP
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@ chip northbridge/intel/haswell
|
|||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM values for eDP
|
||||
register "gpu_cpu_backlight" = "0x00000200"
|
||||
register "gpu_pch_backlight" = "0x04000000"
|
||||
# Set backlight PWM value for eDP
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@ chip northbridge/intel/haswell
|
|||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM values for eDP
|
||||
register "gpu_cpu_backlight" = "0x00000200"
|
||||
register "gpu_pch_backlight" = "0x04000000"
|
||||
# Set backlight PWM value for eDP
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
|
|
|
|||
|
|
@ -12,9 +12,8 @@ chip northbridge/intel/haswell
|
|||
# Enable HDMI Hotplug with 6ms pulse
|
||||
register "gpu_dp_b_hotplug" = "0x06"
|
||||
|
||||
# Set backlight PWM values for eDP
|
||||
register "gpu_cpu_backlight" = "0x00000200"
|
||||
register "gpu_pch_backlight" = "0x04000000"
|
||||
# Set backlight PWM value for eDP
|
||||
register "gpu_pch_backlight_pwm_hz" = "200"
|
||||
|
||||
# Enable Panel and configure power delays
|
||||
register "gpu_panel_port_select" = "1" # eDP
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
chip northbridge/intel/haswell
|
||||
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
|
||||
register "gfx.ndid" = "3"
|
||||
register "gpu_cpu_backlight" = "0x12ba12ba"
|
||||
register "gpu_ddi_e_connected" = "1"
|
||||
register "gpu_dp_b_hotplug" = "4"
|
||||
register "gpu_dp_c_hotplug" = "4"
|
||||
|
|
@ -12,7 +11,7 @@ chip northbridge/intel/haswell
|
|||
register "gpu_panel_power_cycle_delay" = "6"
|
||||
register "gpu_panel_power_down_delay" = "500"
|
||||
register "gpu_panel_power_up_delay" = "2000"
|
||||
register "gpu_pch_backlight" = "0x12ba12ba"
|
||||
register "gpu_pch_backlight_pwm_hz" = "220"
|
||||
device cpu_cluster 0x0 on
|
||||
chip cpu/intel/haswell
|
||||
register "c1_acpower" = "1"
|
||||
|
|
|
|||
|
|
@ -36,8 +36,11 @@ struct northbridge_intel_haswell_config {
|
|||
u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
|
||||
u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
|
||||
|
||||
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
|
||||
u32 gpu_pch_backlight; /* PCH Backlight PWM value */
|
||||
unsigned int gpu_pch_backlight_pwm_hz;
|
||||
enum {
|
||||
GPU_BACKLIGHT_POLARITY_HIGH = 0,
|
||||
GPU_BACKLIGHT_POLARITY_LOW,
|
||||
} gpu_pch_backlight_polarity;
|
||||
|
||||
bool gpu_ddi_e_connected;
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <commonlib/helpers.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
|
@ -347,14 +348,39 @@ static void gma_setup_panel(struct device *dev)
|
|||
gtt_write(PCH_PP_DIVISOR, reg32);
|
||||
}
|
||||
|
||||
/* Enable Backlight if needed */
|
||||
if (conf->gpu_cpu_backlight) {
|
||||
gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE);
|
||||
gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight);
|
||||
}
|
||||
if (conf->gpu_pch_backlight) {
|
||||
gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE);
|
||||
gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight);
|
||||
/* Enforce the PCH PWM function, as so does Linux.
|
||||
The CPU PWM controls are disabled after reset. */
|
||||
if (conf->gpu_pch_backlight_pwm_hz) {
|
||||
/* Reference clock is either 24MHz or 135MHz. We can choose
|
||||
either a 16 or a 128 step increment. Use 16 if we would
|
||||
have less than 100 steps otherwise. */
|
||||
const unsigned int refclock = CONFIG(INTEL_LYNXPOINT_LP) ? 24*MHz : 135*MHz;
|
||||
const unsigned int hz_limit = refclock / 128 / 100;
|
||||
unsigned int pwm_increment, pwm_period;
|
||||
u32 south_chicken2;
|
||||
|
||||
south_chicken2 = gtt_read(SOUTH_CHICKEN2);
|
||||
if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
|
||||
pwm_increment = 16;
|
||||
south_chicken2 |= LPT_PWM_GRANULARITY;
|
||||
} else {
|
||||
pwm_increment = 128;
|
||||
south_chicken2 &= ~LPT_PWM_GRANULARITY;
|
||||
}
|
||||
gtt_write(SOUTH_CHICKEN2, south_chicken2);
|
||||
|
||||
pwm_period = refclock / pwm_increment / conf->gpu_pch_backlight_pwm_hz;
|
||||
printk(BIOS_INFO,
|
||||
"GMA: Setting backlight PWM frequency to %uMHz / %u / %u = %uHz\n",
|
||||
refclock / MHz, pwm_increment, pwm_period,
|
||||
DIV_ROUND_CLOSEST(refclock, pwm_increment * pwm_period));
|
||||
|
||||
/* Start with a 50% duty cycle. */
|
||||
gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2);
|
||||
|
||||
gtt_write(BLC_PWM_PCH_CTL1,
|
||||
(conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 |
|
||||
BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE);
|
||||
}
|
||||
|
||||
/* Get display,pipeline,and DDI registers into a basic sane state */
|
||||
|
|
|
|||
Loading…
Reference in New Issue