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mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select 

This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.

BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.

Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Krishna Prasad Bhat 2019-04-03 15:33:14 +05:30 committed by Martin Roth
parent 78561f481e
commit c2f6c1d544
1 changed files with 7 additions and 7 deletions
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14
src/mainboard/google/hatch/variants/baseboard/gpio.c
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@ -99,8 +99,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */ /* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
/* B19 : GPP_B19 ==> NC */ /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
PAD_NC(GPP_B19, NONE), PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : PCH_SPI_FPMCU_CLK_R */ /* B20 : PCH_SPI_FPMCU_CLK_R */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : PCH_SPI_FPMCU_MISO */ /* B21 : PCH_SPI_FPMCU_MISO */
@ -311,15 +311,15 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_F23, NONE), PAD_NC(GPP_F23, NONE),
/* G0 : SD_CMD */ /* G0 : SD_CMD */
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
/* G1 : SD_DATA0 */ /* G1 : SD_DATA0 */
PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
/* G2 : SD_DATA1 */ /* G2 : SD_DATA1 */
PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
/* G3 : SD_DATA2 */ /* G3 : SD_DATA2 */
PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
/* G4 : SD_DATA3 */ /* G4 : SD_DATA3 */
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
/* G5 : SD_CD# */ /* G5 : SD_CD# */
PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
/* G6 : SD_CLK */ /* G6 : SD_CLK */