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pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper 

Replace the existing, odd looking, unordered definitions used for
LTR configuration with the usual names used by upstream libpci.

TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.

Fixes: Code looked like UEFI copy-pasta. Header file was a mess.
Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2021-03-07 00:29:20 +01:00
parent a768deae73
commit c2ffe89f77
2 changed files with 8 additions and 10 deletions
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8
src/device/pciexp_device.c
View File

@ -140,9 +140,9 @@ static bool pciexp_is_ltr_supported(struct device *dev, unsigned int cap)
{
unsigned int val;
val = pci_read_config16(dev, cap + PCI_EXP_DEV_CAP2_OFFSET);
val = pci_read_config16(dev, cap + PCI_EXP_DEVCAP2);
if (val & LTR_MECHANISM_SUPPORT)
if (val & PCI_EXP_DEVCAP2_LTR)
return true;
return false;
@ -164,10 +164,10 @@ static void pciexp_configure_ltr(struct device *dev)
return;
}
cap += PCI_EXP_DEV_CTL_STS2_CAP_OFFSET;
cap += PCI_EXP_DEVCTL2;
/* Enable LTR for device */
pci_update_config32(dev, cap, ~LTR_MECHANISM_EN, LTR_MECHANISM_EN);
pci_update_config32(dev, cap, ~PCI_EXP_DEV2_LTR, PCI_EXP_DEV2_LTR);
/* Configure Max Snoop Latency */
pciexp_config_max_latency(dev->bus->dev, dev);

10
src/include/device/pci_def.h
View File

@ -386,12 +386,6 @@
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_DEV_CAP2_OFFSET 0x24 /* Device Capabilities 2 offset */
/* LTR mechanism supported.Bit 11 of Device Cap 2 Register */
#define LTR_MECHANISM_SUPPORT (1 << 11)
#define PCI_EXP_DEV_CTL_STS2_CAP_OFFSET 0x28 /* Device Control 2 offset */
/* LTR mechanism enable. Bit 10 of Device Control 2 Register */
#define LTR_MECHANISM_EN (1 << 10)
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
@ -445,6 +439,10 @@
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTSTA 32 /* Root Status */
#define PCI_EXP_DEVCAP2 36 /* Device capabilities 2 */
#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
#define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */
/* Extended Capabilities (PCI-X 2.0 and Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)