amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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@ -1373,27 +1373,32 @@ static void register_fw_addr(amd_bios_type type, char *src_str,
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}
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}
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static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
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uint8_t efs_spi_readmode, uint8_t efs_spi_speed,
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uint8_t efs_spi_micron_flag)
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static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
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embedded_firmware *amd_romsig, uint8_t efs_spi_readmode,
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uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag)
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{
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if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) {
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fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n");
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return 1;
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}
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switch (soc_id) {
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case PLATFORM_STONEYRIDGE:
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/* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
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* Leave as 0xffffffff for first gen */
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if (cb_config->second_gen) {
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amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
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amd_romsig->efs_gen.reserved = 0;
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} else {
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amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
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amd_romsig->efs_gen.reserved = ~0;
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}
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switch (soc_id) {
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case PLATFORM_STONEYRIDGE:
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amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
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amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
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break;
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case PLATFORM_RAVEN:
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case PLATFORM_PICASSO:
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/* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
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* Leave as 0xffffffff for first gen */
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amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
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amd_romsig->efs_gen.reserved = ~0;
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amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
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amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
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switch (efs_spi_micron_flag) {
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@ -1413,8 +1418,6 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig,
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case PLATFORM_CEZANNE:
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case PLATFORM_MENDOCINO:
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case PLATFORM_SABRINA:
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amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
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amd_romsig->efs_gen.reserved = 0;
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amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
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amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
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switch (efs_spi_micron_flag) {
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@ -1471,6 +1474,25 @@ static bool needs_ish(enum platform platform_type)
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return false;
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}
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static bool is_second_gen(enum platform platform_type)
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{
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switch (platform_type) {
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case PLATFORM_STONEYRIDGE:
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case PLATFORM_RAVEN:
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case PLATFORM_PICASSO:
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return false;
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case PLATFORM_RENOIR:
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case PLATFORM_LUCIENNE:
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case PLATFORM_CEZANNE:
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case PLATFORM_SABRINA:
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return true;
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case PLATFORM_UNKNOWN:
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default:
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fprintf(stderr, "Error: Invalid SOC name.\n\n");
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return false;
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}
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}
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int main(int argc, char **argv)
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{
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int c;
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@ -1702,6 +1724,8 @@ int main(int argc, char **argv)
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}
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}
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cb_config.second_gen = is_second_gen(soc_id);
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if (needs_ish(soc_id))
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cb_config.need_ish = true;
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@ -1810,7 +1834,7 @@ int main(int argc, char **argv)
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amd_romsig->xhci_entry = 0;
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if (soc_id != PLATFORM_UNKNOWN) {
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retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode,
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retval = set_efs_table(soc_id, &cb_config, amd_romsig, efs_spi_readmode,
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efs_spi_speed, efs_spi_micron_flag);
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if (retval) {
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fprintf(stderr, "ERROR: Failed to initialize EFS table!\n");
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@ -1822,7 +1846,7 @@ int main(int argc, char **argv)
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if (cb_config.need_ish)
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ctx.address_mode = ADDRESS_MODE_2_REL_TAB;
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else if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN)
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else if (cb_config.second_gen)
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ctx.address_mode = ADDRESS_MODE_1_REL_BIOS;
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else
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ctx.address_mode = ADDRESS_MODE_0_PHY;
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@ -276,6 +276,7 @@ typedef struct _amd_cb_config {
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bool load_mp2_fw;
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bool multi_level;
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bool s0i3;
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bool second_gen;
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bool have_mb_spl;
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bool recovery_ab;
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bool need_ish;
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