From c30981c952ba35f20c280b651f5a61616993af26 Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Fri, 14 Aug 2020 16:54:44 -0600
Subject: [PATCH] soc/amd/picasso: snapshot chipset state early in boot
 sequence

Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.

BUG=b:159947207

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
 src/soc/amd/picasso/romstage.c    | 24 ++++++++++++++++++++++++
 src/soc/amd/picasso/southbridge.c |  6 ++----
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index e7b4b3de99..61782204e3 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -2,6 +2,8 @@
 
 #include <arch/cpu.h>
 #include <acpi/acpi.h>
+#include <amdblocks/acpi.h>
+#include <cbmem.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
 #include <console/uart.h>
@@ -15,6 +17,25 @@
 #include "chip.h"
 #include <fsp/api.h>
 
+static struct acpi_pm_gpe_state chipset_state;
+
+static void fill_chipset_state(void)
+{
+	acpi_fill_pm_gpe_state(&chipset_state);
+}
+
+static void add_chipset_state_cbmem(int unused)
+{
+	struct acpi_pm_gpe_state *state;
+
+	state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
+
+	if (state)
+		acpi_fill_pm_gpe_state(state);
+}
+
+ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem);
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
@@ -81,6 +102,9 @@ asmlinkage void car_stage_entry(void)
 	u32 val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
 
+	/* Snapshot chipset state prior to any FSP call. */
+	fill_chipset_state();
+
 	post_code(0x43);
 	fsp_memory_init(s3_resume);
 	soc_update_mrc_cache();
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index ff8e4360ef..df2d0d0f41 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -314,11 +314,9 @@ void southbridge_init(void *chip_info)
 	i2c_soc_init();
 	sb_init_acpi_ports();
 
-	state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state));
-	if (state) {
-		acpi_fill_pm_gpe_state(state);
+	state = cbmem_find(CBMEM_ID_POWER_STATE);
+	if (state)
 		acpi_pm_gpe_add_events_print_events(state);
-	}
 	acpi_clear_pm_gpe_status();
 
 	al2ahb_clock_gate();