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intel/cannonlake_rvp: Split RVP boards and SPD 

Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.

Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-07-08 18:16:13 -07:00 committed by Aaron Durbin
parent 735779cc9a
commit c319bab3cd
12 changed files with 352 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/mainboard/intel/cannonlake_rvp/Kconfig
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@ -1,14 +1,20 @@
if BOARD_INTEL_CANNONLAKE_RVP if BOARD_INTEL_CANNONLAKE_RVPU || BOARD_INTEL_CANNONLAKE_RVPY
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_CANNONLAKE select SOC_INTEL_CANNONLAKE
select GENERIC_SPD_BIN
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default "intel/cannonlake_rvp" default "intel/cannonlake_rvp"
config VARIANT_DIR
string
default "cnl_u" if BOARD_INTEL_CANNONLAKE_RVPU
default "cnl_y" if BOARD_INTEL_CANNONLAKE_RVPY
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
string string
default "Cannonlake RVP" default "Cannonlake RVP"
@ -17,6 +23,10 @@ config MAINBOARD_VENDOR
string string
default "Intel" default "Intel"
config DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
config IFD_BIN_PATH config IFD_BIN_PATH
string string
depends on HAVE_IFD_BIN depends on HAVE_IFD_BIN
@ -32,4 +42,8 @@ config EC_BIN_PATH
depends on HAVE_EC_BIN depends on HAVE_EC_BIN
default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin" default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ec.bin"
config DIMM_SPD_SIZE
int
default 512
endif endif

6
src/mainboard/intel/cannonlake_rvp/Kconfig.name
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@ -1,2 +1,4 @@
config BOARD_INTEL_CANNONLAKE_RVP config BOARD_INTEL_CANNONLAKE_RVPU
bool "Cannonlake DDR4 RVP" bool "Cannonlake U DDR4 RVP"
config BOARD_INTEL_CANNONLAKE_RVPY
bool "Cannonlake Y LPDDR4 RVP"

21
src/mainboard/intel/cannonlake_rvp/Makefile.inc
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@ -1 +1,20 @@
#Nothing here yet ##
## This file is part of the coreboot project.
##
## Copyright (C) 2013 Google Inc.
## Copyright (C) 2017 Intel Corporation.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
subdirs-y += spd
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

47
src/mainboard/intel/cannonlake_rvp/romstage.c
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@ -14,4 +14,49 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
//Nothing here yet, but file needed for build. #include <arch/byteorder.h>
#include <cbfs.h>
#include <console/console.h>
#include <fsp/api.h>
#include <soc/romstage.h>
#include "spd/spd.h"
#include <string.h>
#include <spd_bin.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg;
mem_cfg = &mupd->FspmConfig;
u8 spd_index;
mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0);
mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1);
mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0);
mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1);
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
mem_cfg->DqPinsInterleaved = 1;
mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */
spd_index = 1;
} else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */
mem_cfg->DqPinsInterleaved = 0;
mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
mem_cfg->ECT = 1; /* Early Command Training Enabled */
spd_index = 2;
}
printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index);
struct region_device spd_rdev;
if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
die("spd.bin not found\n");
mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
/* Memory leak is ok since we have memory mapped boot media */
mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
mem_cfg->RefClk = 0; /* Auto Select CLK freq */
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
}

28
src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc Normal file
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@ -0,0 +1,28 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2014 Google Inc.
## Copyright (C) 2017 Intel Corporation.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += spd_util.c
SPD_BIN = $(obj)/spd.bin
SPD_SOURCES = empty # 0b000
SPD_SOURCES += samsung_ddr4_4GB # 1b001 Dual Channel 4GB
SPD_SOURCES += samsung_lpddr4_8GB # 2b001 Dual Channel 8GB
SPD_SOURCES += empty # 3b011
SPD_SOURCES += empty # 4b100
SPD_SOURCES += empty # 5b101
SPD_SOURCES += empty # 6b110
SPD_SOURCES += empty # 7b111

32
src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex Normal file
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@ -0,0 +1,32 @@
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex Normal file
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@ -0,0 +1,32 @@
23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08
00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 CE 01 16 26 02 FC 5D BE 4D 34 37 31 41 35 31
34 33 45 42 31 2D 43 54 44 20 20 20 20 00 80 CE
00 33 30 32 4A 30 30 30 23 00 01 00 00 00 00 00
01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

32
src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex Normal file
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@ -0,0 +1,32 @@
23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00
48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0
02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

28
src/mainboard/intel/cannonlake_rvp/spd/spd.h Normal file
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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#define RCOMP_TARGET_PARAMS 0x5
void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
#endif

97
src/mainboard/intel/cannonlake_rvp/spd/spd_util.c Normal file
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@ -0,0 +1,97 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/byteorder.h>
#include <cbfs.h>
#include <console/console.h>
#include <stdint.h>
#include <string.h>
#include "spd.h"
void mainboard_fill_dq_map_ch0(void *dq_map_ptr)
{
/* DQ byte map Ch0 */
const u8 dq_map[12] = {
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 ,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
{
/* DQ byte map Ch1 */
const u8 dq_map_u[12] = {
0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
const u8 dq_map_y[12] = {
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));
else
memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));
}
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map Ch0 */
const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
}
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map Ch1 */
const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
}
void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
{
/* Rcomp resistor */
const u16 RcompResistor[3] = { 100, 100, 100 };
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
}
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
{
/* Rcomp target */
static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {
100, 33, 32, 33, 28 };
static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {
80, 40, 40, 40, 30 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(rcomp_strength_ptr, RcompTarget_U,
sizeof(RcompTarget_U));
else
memcpy(rcomp_strength_ptr, RcompTarget_Y,
sizeof(RcompTarget_Y));
}

9
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb Normal file
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@ -0,0 +1,9 @@
chip soc/intel/cannonlake
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
end
end

9
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb Normal file
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@ -0,0 +1,9 @@
chip soc/intel/cannonlake
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
end
end