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drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box 

The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.

BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully

Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brandon Breitenstein 2016-07-27 17:34:45 -07:00 committed by Martin Roth
parent e96543e1fa
commit c31ba0ef52
24 changed files with 583 additions and 517 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/fsp2_0/Kconfig
View File

@ -15,7 +15,7 @@
config PLATFORM_USES_FSP2_0
bool
select UEFI_2_4_BINDING
select UDK_2015_BINDING
help
Include FSP 2.0 wrappers and functionality

14
src/drivers/intel/fsp2_0/debug.c
View File

@ -25,8 +25,8 @@ asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes)
*-----------
*/
void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
const struct FSPM_UPD *fspm_old_upd,
const struct FSPM_UPD *fspm_new_upd)
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd)
{
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
@ -44,7 +44,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", fsp_get_hob_list_ptr());
}
void fsp_debug_after_memory_init(enum fsp_status status)
void fsp_debug_after_memory_init(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspMemoryInit returned 0x%08x\n", status);
@ -72,8 +72,8 @@ void fsp_debug_after_memory_init(enum fsp_status status)
*-----------
*/
void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
const struct FSPS_UPD *fsps_old_upd,
const struct FSPS_UPD *fsps_new_upd)
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd)
{
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
@ -90,7 +90,7 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd);
}
void fsp_debug_after_silicon_init(enum fsp_status status)
void fsp_debug_after_silicon_init(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
@ -120,7 +120,7 @@ void fsp_before_debug_notify(fsp_notify_fn notify,
printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params);
}
void fsp_debug_after_notify(enum fsp_status status)
void fsp_debug_after_notify(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status);

32
src/drivers/intel/fsp2_0/include/fsp/api.h
View File

@ -14,33 +14,9 @@
#define _FSP2_0_API_H_
#include <stddef.h>
#include <fsp/info_header.h>
#include <soc/fsp/FspmUpd.h>
#include <soc/fsp/FspsUpd.h>
#include <fsp/soc_binding.h>
enum fsp_status {
FSP_SUCCESS = 0x00000000,
FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001,
FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002,
FSP_STATUS_RESET_REQUIRED_3 = 0x40000003,
FSP_STATUS_RESET_REQUIRED_4 = 0x40000004,
FSP_STATUS_RESET_REQUIRED_5 = 0x40000005,
FSP_STATUS_RESET_REQUIRED_6 = 0x40000006,
FSP_STATUS_RESET_REQUIRED_7 = 0x40000007,
FSP_STATUS_RESET_REQUIRED_8 = 0x40000008,
FSP_INVALID_PARAMETER = 0x80000002,
FSP_UNSUPPORTED = 0x80000003,
FSP_NOT_READY = 0x80000006,
FSP_DEVICE_ERROR = 0x80000007,
FSP_OUT_OF_RESOURCES = 0x80000009,
FSP_VOLUME_CORRUPTED = 0x8000000a,
FSP_NOT_FOUND = 0x8000000a,
FSP_TIMEOUT = 0x80000012,
FSP_ABORTED = 0x80000015,
FSP_INCOMPATIBLE_VERSION = 0x80000010,
FSP_SECURITY_VIOLATION = 0x8000001a,
FSP_CRC_ERROR = 0x8000001b,
};
#define FSP_SUCCESS EFI_SUCCESS
enum fsp_boot_mode {
FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
@ -64,8 +40,8 @@ void fsp_memory_init(bool s3wake);
void fsp_silicon_init(void);
/* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd);
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd);
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd);
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
/* Callback after processing FSP notify */
void platform_fsp_notify_status(enum fsp_notify_phase phase);

26
src/drivers/intel/fsp2_0/include/fsp/debug.h
View File

@ -16,18 +16,18 @@
/* FSP debug API */
void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
const struct FSPM_UPD *fspm_old_upd,
const struct FSPM_UPD *fspm_new_upd);
void fsp_debug_after_memory_init(enum fsp_status status);
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd);
void fsp_debug_after_memory_init(uint32_t status);
void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
const struct FSPS_UPD *fsps_old_upd,
const struct FSPS_UPD *fsps_new_upd);
void fsp_debug_after_silicon_init(enum fsp_status status);
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd);
void fsp_debug_after_silicon_init(uint32_t status);
void fsp_before_debug_notify(fsp_notify_fn notify,
const struct fsp_notify_params *notify_params);
void fsp_debug_after_notify(enum fsp_status status);
void fspm_display_upd_values(const struct FSPM_UPD *old,
const struct FSPM_UPD *new);
void fsp_debug_after_notify(uint32_t status);
void fspm_display_upd_values(const FSPM_UPD *old,
const FSPM_UPD *new);
void fsp_display_hobs(void);
void fsp_verify_memory_init_hobs(void);
void fsp_print_header_info(const struct fsp_header *hdr);
@ -35,10 +35,10 @@ void fsp_print_header_info(const struct fsp_header *hdr);
/* Callbacks for displaying UPD parameters - place in a separate file
* that is conditionally build with CONFIG_DISPLAY_UPD_DATA.
*/
void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd,
const struct FSPM_UPD *fspm_new_upd);
void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd,
const struct FSPS_UPD *fsps_new_upd);
void soc_display_fspm_upd_params(const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd);
void soc_display_fsps_upd_params(const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd);
/* Callbacks for displaying HOBs - place in a separate file that is
* conditionally build with CONFIG_DISPLAY_HOBS.

30
src/drivers/intel/fsp2_0/include/fsp/soc_binding.h Normal file
View File

@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _FSP2_0_SOC_BINDING_H_
#define _FSP2_0_SOC_BINDING_H_
#pragma pack(push)
/*
* This file is a implementation specific header. i.e. different
* FSP implementations for different chipsets.
*/
#include <Base.h>
#include <soc/fsp/FspmUpd.h>
#include <soc/fsp/FspsUpd.h>
#pragma pack(pop)
#endif

10
src/drivers/intel/fsp2_0/include/fsp/util.h
View File

@ -83,15 +83,15 @@ uintptr_t fsp_load_vbt(void);
* SoC. If the requested status is not a reboot status or unhandled, this
* function does nothing.
*/
void fsp_handle_reset(enum fsp_status status);
void fsp_handle_reset(uint32_t status);
/* SoC/chipset must provide this to handle platform-specific reset codes */
void chipset_handle_reset(enum fsp_status status);
void chipset_handle_reset(uint32_t status);
typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
typedef asmlinkage uint32_t (*fsp_memory_init_fn)
(void *raminit_upd, void **hob_list);
typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)(void *silicon_upd);
typedef asmlinkage enum fsp_status (*fsp_notify_fn)(struct fsp_notify_params *);
typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd);
typedef asmlinkage uint32_t (*fsp_notify_fn)(struct fsp_notify_params *);
#include <fsp/debug.h>
#endif /* _FSP2_0_UTIL_H_ */

12
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -103,7 +103,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
printk(BIOS_SPEW, "Romstage handoff structure not added!\n");
}
static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake,
static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, bool s3wake,
uint32_t fsp_version)
{
const struct mrc_saved_data *mrc_cache;
@ -152,7 +152,7 @@ static enum cb_err check_region_overlap(const struct memranges *ranges,
return CB_SUCCESS;
}
static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd,
static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
bool s3wake, uint32_t fsp_version,
const struct memranges *memmap)
{
@ -183,14 +183,14 @@ static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd,
static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
const struct memranges *memmap)
{
enum fsp_status status;
uint32_t status;
fsp_memory_init_fn fsp_raminit;
struct FSPM_UPD fspm_upd, *upd;
struct FSPM_ARCH_UPD *arch_upd;
FSPM_UPD fspm_upd, *upd;
FSPM_ARCH_UPD *arch_upd;
post_code(0x34);
upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) {
die("Invalid FSPM signature!\n");

3
src/drivers/intel/fsp2_0/notify.c
View File

@ -13,7 +13,6 @@
#include <arch/cpu.h>
#include <bootstate.h>
#include <console/console.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <string.h>
@ -21,7 +20,7 @@
static void fsp_notify(enum fsp_notify_phase phase)
{
enum fsp_status ret;
uint32_t ret;
fsp_notify_fn fspnotify;
struct fsp_notify_params notify_params = { .phase = phase };

6
src/drivers/intel/fsp2_0/silicon_init.c
View File

@ -25,11 +25,11 @@ struct fsp_header fsps_hdr;
static void do_silicon_init(struct fsp_header *hdr)
{
struct FSPS_UPD upd, *supd;
FSPS_UPD upd, *supd;
fsp_silicon_init_fn silicon_init;
enum fsp_status status;
uint32_t status;
supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) {
die("Invalid FSPS signature\n");

12
src/drivers/intel/fsp2_0/upd_display.c
View File

@ -51,15 +51,15 @@ static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old,
/* Display the UPD parameters for MemoryInit */
__attribute__((weak)) void soc_display_fspm_upd_params(
const struct FSPM_UPD *fspm_old_upd,
const struct FSPM_UPD *fspm_new_upd)
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd)
{
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
}
void fspm_display_upd_values(const struct FSPM_UPD *old,
const struct FSPM_UPD *new)
void fspm_display_upd_values(const FSPM_UPD *old,
const FSPM_UPD *new)
{
/* Display the UPD data */
fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd);
@ -68,8 +68,8 @@ void fspm_display_upd_values(const struct FSPM_UPD *old,
/* Display the UPD parameters for SiliconInit */
__attribute__((weak)) void soc_display_fsps_upd_params(
const struct FSPS_UPD *fsps_old_upd,
const struct FSPS_UPD *fsps_new_upd)
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd)
{
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
hexdump(fsps_new_upd, sizeof(*fsps_new_upd));

4
src/drivers/intel/fsp2_0/util.c
View File

@ -92,13 +92,13 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr,
return CB_SUCCESS;
}
static bool fsp_reset_requested(enum fsp_status status)
static bool fsp_reset_requested(uint32_t status)
{
return (status >= FSP_STATUS_RESET_REQUIRED_COLD &&
status <= FSP_STATUS_RESET_REQUIRED_8);
}
void fsp_handle_reset(enum fsp_status status)
void fsp_handle_reset(uint32_t status)
{
if (!fsp_reset_requested(status))
return;

2
src/mainboard/google/reef/romstage.c
View File

@ -162,7 +162,7 @@ static int get_mem_sku(void)
return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
}
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
int mem_sku = get_mem_sku();

8
src/mainboard/intel/amenia/romstage.c
View File

@ -17,7 +17,7 @@
#include <soc/romstage.h>
#include <string.h>
#include <soc/fsp/FspmUpd.h>
#include <fsp/soc_binding.h>
/* Channel 0 PHY to DUnit DQ mapping */
static const uint8_t swizzling_ch0_amenia[] = {
@ -43,7 +43,7 @@ static const uint8_t swizzling_ch3_amenia[] = {
17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30,
};
static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg)
static void amenia_fill_memory_params(FSP_M_CONFIG *cfg)
{
cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */
cfg->DIMM0SPDAddress = 0;
@ -87,9 +87,9 @@ static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg)
sizeof(swizzling_ch3_amenia));
}
void mainboard_memory_init_params(struct FSPM_UPD *memupd)
void mainboard_memory_init_params(FSPM_UPD *memupd)
{
struct FSP_M_CONFIG *cfg = &memupd->FspmConfig;
FSP_M_CONFIG *cfg = &memupd->FspmConfig;
cfg->Package = 1; /* 0x1:BGA */
cfg->MemoryDown = 1;

8
src/mainboard/intel/apollolake_rvp/romstage.c
View File

@ -18,7 +18,7 @@
#include <soc/romstage.h>
#include <string.h>
#include <fsp/api.h>
#include <soc/fsp/FspmUpd.h>
#include <fsp/soc_binding.h>
static const uint8_t swizzling_rvp1[] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
@ -45,7 +45,7 @@ static const uint8_t swizzling3_rvp2[] = {
15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28,
};
static void rvp1_fill_memory_params(struct FSPM_UPD *mupd)
static void rvp1_fill_memory_params(FSPM_UPD *mupd)
{
mupd->FspmConfig.Profile = 33;
mupd->FspmConfig.DIMM0SPDAddress = 0xa0;
@ -72,7 +72,7 @@ static void rvp1_fill_memory_params(struct FSPM_UPD *mupd)
memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1));
}
static void rvp2_fill_memory_params(struct FSPM_UPD *mupd)
static void rvp2_fill_memory_params(FSPM_UPD *mupd)
{
mupd->FspmConfig.Profile = 5;
mupd->FspmConfig.DIMM0SPDAddress = 0;
@ -103,7 +103,7 @@ static void rvp2_fill_memory_params(struct FSPM_UPD *mupd)
sizeof(swizzling3_rvp2));
}
void mainboard_memory_init_params(struct FSPM_UPD *mupd)
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
mupd->FspmConfig.Package = 0;
mupd->FspmConfig.MemoryDown = 1;

8
src/soc/intel/apollolake/chip.c
View File

@ -231,7 +231,7 @@ static void soc_final(void *data)
global_reset_lock();
}
static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) {
switch (dev->path.pci.devfn) {
case ISH_DEVFN:
@ -335,7 +335,7 @@ static void disable_dev(struct device *dev, struct FSP_S_CONFIG *silconfig) {
}
}
static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
static void parse_devicetree(FSP_S_CONFIG *silconfig)
{
struct device *dev = NB_DEV_ROOT;
@ -350,9 +350,9 @@ static void parse_devicetree(struct FSP_S_CONFIG *silconfig)
}
}
void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
/* Load VBT before devicetree-specific config. */

48
src/soc/intel/apollolake/include/FspUpd.h Normal file
View File

@ -0,0 +1,48 @@
/** @file
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
This file is automatically generated. Please do NOT modify !!!
**/
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#pragma pack(push, 1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#pragma pack(pop)
#endif

6
src/soc/intel/apollolake/include/soc/fsp/FspUpd.h
View File

@ -33,10 +33,16 @@ are permitted provided that the following conditions are met:
#ifndef __FSPUPD_H__
#define __FSPUPD_H__
#include <FspEas.h>
#pragma pack(push, 1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#pragma pack(pop)
#endif

278
src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h
View File

@ -33,87 +33,89 @@ are permitted provided that the following conditions are met:
#ifndef __FSPMUPD_H__
#define __FSPMUPD_H__
#include "FspUpd.h"
#include <fsp/upd.h>
#include <FspUpd.h>
#pragma pack(push, 1)
#define MAX_CHANNELS_NUM 4
#define MAX_DIMMS_NUM 1
struct DIMM_INFO {
uint8_t DimmId;
uint32_t SizeInMb;
uint16_t MfgId;
typedef struct {
UINT8 DimmId;
UINT32 SizeInMb;
UINT16 MfgId;
/** Module part number for DRR3 is 18 bytes
but DRR4 is 20 bytes as per JEDEC Spec, so
reserving 20 bytes **/
uint8_t ModulePartNum[20];
} __attribute__((packed));
UINT8 ModulePartNum[20];
} DIMM_INFO;
struct CHANNEL_INFO {
uint8_t ChannelId;
uint8_t DimmCount;
struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} __attribute__((packed));
typedef struct {
UINT8 ChannelId;
UINT8 DimmCount;
DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
} CHANNEL_INFO;
struct FSP_SMBIOS_MEMORY_INFO {
uint8_t Revision;
uint8_t DataWidth;
typedef struct {
UINT8 Revision;
UINT8 DataWidth;
/** As defined in SMBIOS 3.0 spec
Section 7.18.2 and Table 75
**/
uint16_t MemoryType;
uint16_t MemoryFrequencyInMHz;
UINT16 MemoryType;
UINT16 MemoryFrequencyInMHz;
/** As defined in SMBIOS 3.0 spec
Section 7.17.3 and Table 72
**/
uint8_t ErrorCorrectionType;
uint8_t ChannelCount;
struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} __attribute__((packed));
UINT8 ErrorCorrectionType;
UINT8 ChannelCount;
CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
} FSP_SMBIOS_MEMORY_INFO;
/** Fsp M Configuration
**/
struct FSP_M_CONFIG {
typedef struct {
/** Offset 0x0040 - Debug Serial Port Base address
Debug serial port base address. This option will be used only when the 'Serial Port
Debug Device' option is set to 'External Device'. 0x00000000(Default).
**/
uint32_t SerialDebugPortAddress;
UINT32 SerialDebugPortAddress;
/** Offset 0x0044 - Debug Serial Port Type
16550 compatible debug serial port resource type. NONE means no serial port support.
0x02:MMIO(Default).
0:NONE, 1:I/O, 2:MMIO
**/
uint8_t SerialDebugPortType;
UINT8 SerialDebugPortType;
/** Offset 0x0045 - Serial Port Debug Device
Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
Base' options will be ignored. 0x02:SOC UART2(Default).
0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
**/
uint8_t SerialDebugPortDevice;
UINT8 SerialDebugPortDevice;
/** Offset 0x0046 - Debug Serial Port Stride Size
Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
0:1, 2:4
**/
uint8_t SerialDebugPortStrideSize;
UINT8 SerialDebugPortStrideSize;
/** Offset 0x0047 - Memory Fast Boot
Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
uint8_t MrcFastBoot;
UINT8 MrcFastBoot;
/** Offset 0x0048 - Integrated Graphics Device
Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
uint8_t Igd;
UINT8 Igd;
/** Offset 0x0049 - DVMT Pre-Allocated
Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
@ -122,35 +124,35 @@ struct FSP_M_CONFIG {
MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
0x0F:480 MB, 0x10:512 MB
**/
uint8_t IgdDvmt50PreAlloc;
UINT8 IgdDvmt50PreAlloc;
/** Offset 0x004A - Aperture Size
Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
0x2:256 MB, 0x3:512 MB.
0x1:128 MB, 0x2:256 MB, 0x3:512 MB
**/
uint8_t IgdApertureSize;
UINT8 IgdApertureSize;
/** Offset 0x004B - GTT Size
Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
MB(Default).
0x1:2 MB, 0x2:4 MB, 0x3:8 MB
**/
uint8_t GttSize;
UINT8 GttSize;
/** Offset 0x004C - Primary Display
Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
0x2:IGD, 0x3:PCI
0x0:AUTO, 0x2:IGD, 0x3:PCI
**/
uint8_t PrimaryVideoAdaptor;
UINT8 PrimaryVideoAdaptor;
/** Offset 0x004D - Package
NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L
is being used. 0x00(Default).
0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD
**/
uint8_t Package;
UINT8 Package;
/** Offset 0x004E - Profile
Profile list. 0x19(Default).
@ -167,127 +169,127 @@ struct FSP_M_CONFIG {
0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,
0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
**/
uint8_t Profile;
UINT8 Profile;
/** Offset 0x004F - MemoryDown
Memory Down. 0x0(Default).
0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
**/
uint8_t MemoryDown;
UINT8 MemoryDown;
/** Offset 0x0050 - DDR3LPageSize
NOTE: Only for memory down or downgrade DDR3L frequency. 0x01:1KB(Default), 0x02:2KB.
0x1:1KB, 0x2:2KB
**/
uint8_t DDR3LPageSize;
UINT8 DDR3LPageSize;
/** Offset 0x0051 - DDR3LASR
NOTE: Only for memory down. 0x00:Not Supported(Default), 0x01:Supported.
0x0:Not Supported, 0x1:Supported
**/
uint8_t DDR3LASR;
UINT8 DDR3LASR;
/** Offset 0x0052 - ScramblerSupport
Scrambler Support. 0x00:Not Supported, 0x01:Supported(Default).
$EN_DIS
**/
uint8_t ScramblerSupport;
UINT8 ScramblerSupport;
/** Offset 0x0053 - ChannelHashMask
Channel Hash Mask. 0x00(Default).
**/
uint16_t ChannelHashMask;
UINT16 ChannelHashMask;
/** Offset 0x0055 - SliceHashMask
Slice Hash Mask. 0x00(Default).
**/
uint16_t SliceHashMask;
UINT16 SliceHashMask;
/** Offset 0x0057 - InterleavedMode
Interleaved Mode. 0x00:Disable(Default), 0x02:Enable.
0x0:Disable, 0x2:Enable
**/
uint8_t InterleavedMode;
UINT8 InterleavedMode;
/** Offset 0x0058 - ChannelsSlicesEnable
Channels Slices Enable. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
uint8_t ChannelsSlicesEnable;
UINT8 ChannelsSlicesEnable;
/** Offset 0x0059 - MinRefRate2xEnable
Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
0x01:Enable.
$EN_DIS
**/
uint8_t MinRefRate2xEnable;
UINT8 MinRefRate2xEnable;
/** Offset 0x005A - DualRankSupportEnable
Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
$EN_DIS
**/
uint8_t DualRankSupportEnable;
UINT8 DualRankSupportEnable;
/** Offset 0x005B - RmtMode
Rank Margin Tool Mode. 0x00(Default).
$EN_DIS
**/
uint8_t RmtMode;
UINT8 RmtMode;
/** Offset 0x005C - MemorySizeLimit
Memory Size Limit: This value is used to restrict the total amount of memory and
the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
**/
uint16_t MemorySizeLimit;
UINT16 MemorySizeLimit;
/** Offset 0x005E - LowMemoryMaxValue
Low Memory Max Value: This value is used to restrict the amount of memory below
4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
= 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
**/
uint16_t LowMemoryMaxValue;
UINT16 LowMemoryMaxValue;
/** Offset 0x0060 - DisableFastBoot
00:Disabled Used saved training data (if valid)(Default), 01:Enabled; Full re-train
of memory.
$EN_DIS
**/
uint8_t DisableFastBoot;
UINT8 DisableFastBoot;
/** Offset 0x0061 - HighMemoryMaxValue
High Memory Max Value: This value is used to restrict the amount of memory above
4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
**/
uint16_t HighMemoryMaxValue;
UINT16 HighMemoryMaxValue;
/** Offset 0x0063 - DIMM0SPDAddress
DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
**/
uint8_t DIMM0SPDAddress;
UINT8 DIMM0SPDAddress;
/** Offset 0x0064 - DIMM1SPDAddress
DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
**/
uint8_t DIMM1SPDAddress;
UINT8 DIMM1SPDAddress;
/** Offset 0x0065 - Ch0_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch0 rank. 0x00(Default).
**/
uint8_t Ch0_RankEnable;
UINT8 Ch0_RankEnable;
/** Offset 0x0066 - Ch0_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default).
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
uint8_t Ch0_DeviceWidth;
UINT8 Ch0_DeviceWidth;
/** Offset 0x0067 - Ch0_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
uint8_t Ch0_DramDensity;
UINT8 Ch0_DramDensity;
/** Offset 0x0068 - Ch0_Option
Rank Select Interleaving Enable. See Address Mapping section for full description.
@ -297,22 +299,22 @@ struct FSP_M_CONFIG {
This register specifies the address mapping to be used: 00:1KB (A), 01:2KB (B).
0x03(Default).
**/
uint8_t Ch0_Option;
UINT8 Ch0_Option;
/** Offset 0x0069 - Ch0_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
uint8_t Ch0_OdtConfig;
UINT8 Ch0_OdtConfig;
/** Offset 0x006A - Ch0_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
uint8_t Ch0_TristateClk1;
UINT8 Ch0_TristateClk1;
/** Offset 0x006B - Ch0_Mode2N
2N Mode. 0x00(Default).
**/
uint8_t Ch0_Mode2N;
UINT8 Ch0_Mode2N;
/** Offset 0x006C - Ch0_OdtLevels
Rank Select Interleaving Enable. See Address Mapping section for full description.
@ -321,24 +323,24 @@ struct FSP_M_CONFIG {
0:Bank Address Hashing disabled, 1:Bank Address Hashing enabled. [3:2] Reserved.
[5:4] This register specifies the address mapping to be used:00:1KB (A), 01:2KB (B).
**/
uint8_t Ch0_OdtLevels;
UINT8 Ch0_OdtLevels;
/** Offset 0x006D - Ch1_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch1 rank.
**/
uint8_t Ch1_RankEnable;
UINT8 Ch1_RankEnable;
/** Offset 0x006E - Ch1_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00(Default).
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
uint8_t Ch1_DeviceWidth;
UINT8 Ch1_DeviceWidth;
/** Offset 0x006F - Ch1_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
uint8_t Ch1_DramDensity;
UINT8 Ch1_DramDensity;
/** Offset 0x0070 - Ch1_Option
Rank Select Interleaving Enable. See Address Mapping section for full description.
@ -348,45 +350,45 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used: 00:1KB (A), 01:2KB
(B), 0x03(Default).
**/
uint8_t Ch1_Option;
UINT8 Ch1_Option;
/** Offset 0x0071 - Ch1_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
uint8_t Ch1_OdtConfig;
UINT8 Ch1_OdtConfig;
/** Offset 0x0072 - Ch1_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
uint8_t Ch1_TristateClk1;
UINT8 Ch1_TristateClk1;
/** Offset 0x0073 - Ch1_Mode2N
2N Mode. 0x00(Default).
**/
uint8_t Ch1_Mode2N;
UINT8 Ch1_Mode2N;
/** Offset 0x0074 - Ch1_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH. 3:ODT_AB_HIGH_LOW.
**/
uint8_t Ch1_OdtLevels;
UINT8 Ch1_OdtLevels;
/** Offset 0x0075 - Ch2_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch2 rank.
**/
uint8_t Ch2_RankEnable;
UINT8 Ch2_RankEnable;
/** Offset 0x0076 - Ch2_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1.
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
uint8_t Ch2_DeviceWidth;
UINT8 Ch2_DeviceWidth;
/** Offset 0x0077 - Ch2_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00(Default).
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
uint8_t Ch2_DramDensity;
UINT8 Ch2_DramDensity;
/** Offset 0x0078 - Ch2_Option
Rank Select Interleaving Enable. See Address Mapping section for full description..
@ -396,47 +398,47 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used:. 00:1KB (A)(Default).
01:2KB (B).
**/
uint8_t Ch2_Option;
UINT8 Ch2_Option;
/** Offset 0x0079 - Ch2_OdtConfig
ODT configuration control. 0:WEAK_ODT_CONFIG(Default), 1:STRONG_ODT_CONFIG.
**/
uint8_t Ch2_OdtConfig;
UINT8 Ch2_OdtConfig;
/** Offset 0x007A - Ch2_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
uint8_t Ch2_TristateClk1;
UINT8 Ch2_TristateClk1;
/** Offset 0x007B - Ch2_Mode2N
2N Mode. 0x00(Default).
**/
uint8_t Ch2_Mode2N;
UINT8 Ch2_Mode2N;
/** Offset 0x007C - Ch2_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW.
**/
uint8_t Ch2_OdtLevels;
UINT8 Ch2_OdtLevels;
/** Offset 0x007D - Ch3_RankEnable
NOTE: Only for memory down. Set to 1 to enable Ch3 rank. 0x00(Default).
**/
uint8_t Ch3_RankEnable;
UINT8 Ch3_RankEnable;
/** Offset 0x007E - Ch3_DeviceWidth
NOTE: Only for memory down. DRAM Device Data Width populated on Ranks 0 and 1. 0x00:x8(Default),
0x01:x16, 0x02:x32, 0x03:x64.
0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
**/
uint8_t Ch3_DeviceWidth;
UINT8 Ch3_DeviceWidth;
/** Offset 0x007F - Ch3_DramDensity
NOTE: Only for memory down. DRAM Device Density populated on Ranks 0 and 1. 0x00:4Gb(Default),
0x01:6Gb, 0x02:8Gb, 0x03:12Gb, 0x04:16Gb.
0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
**/
uint8_t Ch3_DramDensity;
UINT8 Ch3_DramDensity;
/** Offset 0x0080 - Ch3_Option
Rank Select Interleaving Enable. See Address Mapping section for full description..
@ -446,272 +448,274 @@ struct FSP_M_CONFIG {
[5:4] This register specifies the address mapping to be used:. 00 - 1KB (A). 01
- 2KB (B).
**/
uint8_t Ch3_Option;
UINT8 Ch3_Option;
/** Offset 0x0081 - Ch3_OdtConfig
ODT configuration control.. 0:WEAK_ODT_CONFIG(Default). 1:STRONG_ODT_CONFIG.
**/
uint8_t Ch3_OdtConfig;
UINT8 Ch3_OdtConfig;
/** Offset 0x0082 - Ch3_TristateClk1
Parameter used to determine whether to tristate CLK1. 0x00(Default).
**/
uint8_t Ch3_TristateClk1;
UINT8 Ch3_TristateClk1;
/** Offset 0x0083 - Ch3_Mode2N
2N Mode. 0x00(Default).
**/
uint8_t Ch3_Mode2N;
UINT8 Ch3_Mode2N;
/** Offset 0x0084 - Ch3_OdtLevels
Parameter used to determine if ODT will be held high or low. 0:Use MRC default(Default),
1:ODT_AB_HIGH_HIGH, 3:ODT_AB_HIGH_LOW.
**/
uint8_t Ch3_OdtLevels;
UINT8 Ch3_OdtLevels;
/** Offset 0x0085 - RmtCheckRun
RmtCheckRun: 0x00(Default).
**/
uint8_t RmtCheckRun;
UINT8 RmtCheckRun;
/** Offset 0x0086 - Ch0_Bit_swizzling
Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
uint8_t Ch0_Bit_swizzling[32];
UINT8 Ch0_Bit_swizzling[32];
/** Offset 0x00A6 - Ch1_Bit_swizzling
Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
uint8_t Ch1_Bit_swizzling[32];
UINT8 Ch1_Bit_swizzling[32];
/** Offset 0x00C6 - Ch2_Bit_swizzling
Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
uint8_t Ch2_Bit_swizzling[32];
UINT8 Ch2_Bit_swizzling[32];
/** Offset 0x00E6 - Ch3_Bit_swizzling
Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
**/
uint8_t Ch3_Bit_swizzling[32];
UINT8 Ch3_Bit_swizzling[32];
/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold
RmtMarginCheckScaleHighThreshold. 0x0000(Default).
**/
uint16_t RmtMarginCheckScaleHighThreshold;
UINT16 RmtMarginCheckScaleHighThreshold;
/** Offset 0x0108 - MsgLevelMask
MsgLevelMask. 0x00000000(Default).
**/
uint32_t MsgLevelMask;
UINT32 MsgLevelMask;
/** Offset 0x010C
**/
uint32_t UnusedUpdSpace0;
UINT32 UnusedUpdSpace0;
/** Offset 0x0110 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
Number of Entries in PreMem GPIO Table. 0(Default).
**/
uint8_t PreMemGpioTableEntryNum;
UINT8 PreMemGpioTableEntryNum;
/** Offset 0x0111 - PreMem GPIO Pin Number for each table
Number of Pins in each PreMem GPIO Table. 0(Default).
**/
uint8_t PreMemGpioTablePinNum[4];
UINT8 PreMemGpioTablePinNum[4];
/** Offset 0x0115 - PreMem GPIO Table Pointer
Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
**/
uint32_t PreMemGpioTablePtr;
UINT32 PreMemGpioTablePtr;
/** Offset 0x0119 - Enhance the port 8xh decoding
Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
uint8_t EnhancePort8xhDecoding;
UINT8 EnhancePort8xhDecoding;
/** Offset 0x011A - OEM File Loading Address
Determine the memory base address to load a specified file from CSE file system
after memory is available.
**/
uint32_t OemLoadingBase;
UINT32 OemLoadingBase;
/** Offset 0x011E - OEM File Name to Load
Specify a file name to load from CSE file system after memory is available. Empty
indicates no file needs to be loaded.
**/
uint8_t OemFileName[16];
UINT8 OemFileName[16];
/** Offset 0x012E - SPD Data Write
Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
uint8_t SpdWriteEnable;
UINT8 SpdWriteEnable;
/** Offset 0x012F - MRC Training Data Saving
Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
uint8_t MrcDataSaving;
UINT8 MrcDataSaving;
/** Offset 0x0130 - eMMC Trace Length
Select eMMC trace length to load OEM file from when loading OEM file name is specified.
0x0:Long(Default), 0x1:Short.
0x0:Long, 0x1:Short
**/
uint8_t eMMCTraceLen;
UINT8 eMMCTraceLen;
/** Offset 0x0131
**/
void* MrcBootDataPtr;
VOID* MrcBootDataPtr;
/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
CSE. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
uint8_t SkipCseRbp;
UINT8 SkipCseRbp;
/** Offset 0x0136 - Npk Enable
Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default).
0:Disable, 1:Enable, 2:Debugger, 3:Auto
**/
uint8_t NpkEn;
UINT8 NpkEn;
/** Offset 0x0137 - FW Trace Enable
Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
uint8_t FwTraceEn;
UINT8 FwTraceEn;
/** Offset 0x0138 - FW Trace Destination
FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
4-NPK_TRACE_TO_PTI(Default).
**/
uint8_t FwTraceDestination;
UINT8 FwTraceDestination;
/** Offset 0x0139 - NPK Recovery Dump
Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
uint8_t RecoverDump;
UINT8 RecoverDump;
/** Offset 0x013A - Memory Region 0 Buffer WrapAround
Memory Region 0 Buffer WrapAround. 0-n0-wrap, 1-warp(Default).
Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
uint8_t Msc0Wrap;
UINT8 Msc0Wrap;
/** Offset 0x013B - Memory Region 1 Buffer WrapAround
Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
**/
uint8_t Msc1Wrap;
UINT8 Msc1Wrap;
/** Offset 0x013C - Memory Region 0 Buffer Size
Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
uint32_t Msc0Size;
UINT32 Msc0Size;
/** Offset 0x0140 - Memory Region 1 Buffer Size
Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
6-512MB, 7-1GB.
**/
uint32_t Msc1Size;
UINT32 Msc1Size;
/** Offset 0x0144 - PTI Mode
PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
**/
uint8_t PtiMode;
UINT8 PtiMode;
/** Offset 0x0145 - PTI Training
PTI Training. 0-off(Default), 1-6=1-6.
**/
uint8_t PtiTraining;
UINT8 PtiTraining;
/** Offset 0x0146 - PTI Speed
PTI Speed. 0-full, 1-half, 2-quarter(Default).
**/
uint8_t PtiSpeed;
UINT8 PtiSpeed;
/** Offset 0x0147 - Punit Message Level
Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
uint8_t PunitMlvl;
UINT8 PunitMlvl;
/** Offset 0x0148 - PMC Message Level
PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
**/
uint8_t PmcMlvl;
UINT8 PmcMlvl;
/** Offset 0x0149 - SW Trace Enable
Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
uint8_t SwTraceEn;
UINT8 SwTraceEn;
/** Offset 0x014A - Periodic Retraining Disable
Option to disable LPDDR4 Periodic Retraining. 0x00:Disable(Default), 0x01:Enable.
$EN_DIS
**/
uint8_t PeriodicRetrainingDisable;
UINT8 PeriodicRetrainingDisable;
/** Offset 0x014B
**/
uint8_t ReservedFspmUpd[5];
} __attribute__((packed));
UINT8 ReservedFspmUpd[5];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
**/
struct FSP_M_TEST_CONFIG {
typedef struct {
/** Offset 0x0150
**/
uint32_t Signature;
UINT32 Signature;
/** Offset 0x0154
**/
uint8_t ReservedFspmTestUpd[28];
} __attribute__((packed));
UINT8 ReservedFspmTestUpd[28];
} FSP_M_TEST_CONFIG;
/** Fsp M Restricted Configuration
**/
struct FSP_M_RESTRICTED_CONFIG {
typedef struct {
/** Offset 0x0170
**/
uint32_t Signature;
UINT32 Signature;
/** Offset 0x0174
**/
uint8_t ReservedFspmRestrictedUpd[138];
} __attribute__((packed));
UINT8 ReservedFspmRestrictedUpd[138];
} FSP_M_RESTRICTED_CONFIG;
/** Fsp M UPD Configuration
**/
struct FSPM_UPD {
typedef struct {
/** Offset 0x0000
**/
struct FSP_UPD_HEADER FspUpdHeader;
FSP_UPD_HEADER FspUpdHeader;
/** Offset 0x0020
**/
struct FSPM_ARCH_UPD FspmArchUpd;
FSPM_ARCH_UPD FspmArchUpd;
/** Offset 0x0040
**/
struct FSP_M_CONFIG FspmConfig;
FSP_M_CONFIG FspmConfig;
/** Offset 0x0150
**/
struct FSP_M_TEST_CONFIG FspmTestConfig;
FSP_M_TEST_CONFIG FspmTestConfig;
/** Offset 0x0170
**/
struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig;
/** Offset 0x01FE
**/
uint16_t UpdTerminator;
} __attribute__((packed));
UINT16 UpdTerminator;
} FSPM_UPD;
#pragma pack(pop)
#endif

552
src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h
View File

File diff suppressed because it is too large Load Diff

9
src/soc/intel/apollolake/include/soc/meminit.h
View File

@ -18,6 +18,7 @@
#include <stddef.h>
#include <stdint.h>
#include <fsp/soc_binding.h>
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
@ -77,13 +78,11 @@ struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
struct FSP_M_CONFIG;
/*
* Initialize default LPDDR4 settings with provided speed. No logical channels
* are enabled. Subsequent calls to logical channel enabling are required.
*/
void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed);
void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed);
/*
* Enable logical channel providing the full lpddr4_swizzle_config to
@ -91,7 +90,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed);
* memory width per logical channel -- i.e. 2 physical channels are configured
* to the memory reference code.
*/
void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg);
@ -115,7 +114,7 @@ struct lpddr4_cfg {
* Initialize LPDDR4 settings by the provided lpddr4_cfg information and sku id.
* The sku id is an index into the sku array within the lpddr4_cfg struct.
*/
void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
const struct lpddr4_cfg *lpcfg, size_t sku_id);
void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku);

2
src/soc/intel/apollolake/include/soc/romstage.h
View File

@ -21,7 +21,7 @@
#include <arch/cpu.h>
#include <fsp/api.h>
void mainboard_memory_init_params(struct FSPM_UPD *mupd);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void mainboard_save_dimm_info(void);
#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */

20
src/soc/intel/apollolake/meminit.c
View File

@ -19,10 +19,10 @@
#include <smbios.h>
#include <soc/meminit.h>
#include <stddef.h> /* required for FspmUpd.h */
#include <soc/fsp/FspmUpd.h>
#include <fsp/soc_binding.h>
#include <string.h>
static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg)
static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
{
/* Enable memory down BGA since it's the only LPDDR4 packaging. */
cfg->Package = 1;
@ -80,7 +80,7 @@ static void set_lpddr4_defaults(struct FSP_M_CONFIG *cfg)
cfg->Ch3_OdtConfig = 0;
}
void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed)
void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
{
uint8_t profile;
@ -107,7 +107,7 @@ void meminit_lpddr4(struct FSP_M_CONFIG *cfg, int speed)
set_lpddr4_defaults(cfg);
}
static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
static void enable_logical_chan0(FSP_M_CONFIG *cfg,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@ -152,7 +152,7 @@ static void enable_logical_chan0(struct FSP_M_CONFIG *cfg,
memcpy(&cfg->Ch1_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz);
}
static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
static void enable_logical_chan1(FSP_M_CONFIG *cfg,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@ -197,7 +197,7 @@ static void enable_logical_chan1(struct FSP_M_CONFIG *cfg,
memcpy(&cfg->Ch3_Bit_swizzling[24], &chan->dqs[LP4_DQS3], sz);
}
void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
void meminit_lpddr4_enable_channel(FSP_M_CONFIG *cfg, int logical_chan,
int rank_density, int dual_rank,
const struct lpddr4_swizzle_cfg *scfg)
{
@ -220,7 +220,7 @@ void meminit_lpddr4_enable_channel(struct FSP_M_CONFIG *cfg, int logical_chan,
}
}
void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg,
const struct lpddr4_cfg *lpcfg, size_t sku_id)
{
const struct lpddr4_sku *sku;
@ -262,11 +262,11 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)
{
int channel, dimm, dimm_max, index;
size_t hob_size;
const struct DIMM_INFO *src_dimm;
const DIMM_INFO *src_dimm;
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
const struct CHANNEL_INFO *channel_info;
const struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
const CHANNEL_INFO *channel_info;
const FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
if (mem_sku >= lp4cfg->num_skus) {
printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",

2
src/soc/intel/apollolake/reset.c
View File

@ -59,7 +59,7 @@ void reset_prepare(void)
printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
}
void chipset_handle_reset(enum fsp_status status)
void chipset_handle_reset(uint32_t status)
{
switch(status) {
case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */

6
src/soc/intel/apollolake/romstage.c
View File

@ -133,7 +133,7 @@ asmlinkage void car_stage_entry(void)
run_postcar_phase(&pcf);
}
static void fill_console_params(struct FSPM_UPD *mupd)
static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE;
@ -148,7 +148,7 @@ static void fill_console_params(struct FSPM_UPD *mupd)
}
}
void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)
{
fill_console_params(mupd);
mainboard_memory_init_params(mupd);
@ -167,7 +167,7 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
}
__attribute__ ((weak))
void mainboard_memory_init_params(struct FSPM_UPD *mupd)
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}