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mb/google/hatch: Add overridetree to hatch variant 

Add serialio settings to hatch.  Only applies to CML.

BUG=b:128347800
BRANCH=None
TEST=abuild

Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shelley Chen 2019-03-20 13:48:00 -07:00 committed by Patrick Georgi
parent 5eeee58ca2
commit c325fa1312
2 changed files with 22 additions and 0 deletions
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4
src/mainboard/google/hatch/Kconfig
View File

@ -80,6 +80,10 @@ config MAX_CPUS
int
default 8
config OVERRIDE_DEVICETREE
string
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH_WHL
config TPM_TIS_ACPI_INTERRUPT
int
default 53 # GPE0_DW1_21 (GPP_C21)

18
src/mainboard/google/hatch/variants/hatch/overridetree.cb Normal file
View File

@ -0,0 +1,18 @@
chip soc/intel/cannonlake
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoPci,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
end