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soc/intel/tigerlake: Disable image clocks 

TGL FSP does just pin mux for image clock pins by UPD and image clocks
are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder.
Disable image clocks by UPD for bypassing FSP pin mux and do pin mux
in gpio.c according to board design.

BUG=none
BRANCH=none
TEST=Build and boot to OS

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-01-24 17:02:08 -08:00 committed by Patrick Georgi
parent 03b20350e3
commit c332a47c54
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
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@ -102,6 +102,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
/* Image clock: disable all clocks for bypassing FSP pin mux */
memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
/* Enable Hyper Threading */ /* Enable Hyper Threading */
m_cfg->HyperThreading = 1; m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */ /* Disable Lock PCU Thermal Management registers */