soc/intel/common: Add Intel SRAM common code support
Add SRAM code support in intel/common/block to read and use fixed resources on BAR0 and BAR2 for SRAM. Change-Id: I7870a3ca09ac7b57eb551d5eb42d8361d22f362a Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/22607 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_INTEL_COMMON_BLOCK_SRAM_H
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#define SOC_INTEL_COMMON_BLOCK_SRAM_H
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#include <device/device.h>
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/* This function is specific to soc and defined as common weak function */
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void soc_sram_init(struct device *dev);
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#endif /* SOC_INTEL_COMMON_BLOCK_SRAM_H */
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config SOC_INTEL_COMMON_BLOCK_SRAM
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bool
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help
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Intel Processor common SRAM support
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ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SRAM) += sram.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <intelblocks/sram.h>
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#include <soc/iomap.h>
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__attribute__((weak)) void soc_sram_init(struct device *dev) { /* no-op */ }
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static void sram_read_resources(struct device *dev)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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res = new_resource(dev, PCI_BASE_ADDRESS_0);
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res->base = SRAM_BASE_0;
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res->size = SRAM_SIZE_0;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, PCI_BASE_ADDRESS_2);
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res->base = SRAM_BASE_2;
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res->size = SRAM_SIZE_2;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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static const struct device_operations device_ops = {
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.read_resources = sram_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = soc_sram_init,
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};
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static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_APL_SRAM,
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PCI_DEVICE_ID_INTEL_GLK_SRAM,
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0,
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};
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static const struct pci_driver sram __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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