soc/{amd,intel}/chip: Use local include for chip.h
Change-Id: Ic1fcbf4b54b7d0b5cda04ca9f7fc145050c867b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
parent
9df72e0471
commit
c3385070d6
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@ -13,7 +13,6 @@
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <bootstate.h>
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#include <console/console.h>
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#include <cpu/amd/mtrr.h>
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@ -30,6 +29,8 @@
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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#include "chip.h"
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/* Supplied by i2c.c */
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extern struct device_operations stoneyridge_i2c_mmio_ops;
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extern const char *i2c_acpi_name(const struct device *dev);
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@ -13,13 +13,11 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <console/console.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/lapic_def.h>
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#include <string.h>
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#include <arch/bert_storage.h>
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#include "chip.h"
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static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
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u32 io_min, u32 io_max)
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{
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@ -24,7 +24,6 @@
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <chip.h>
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#include <program_loading.h>
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#include <romstage_handoff.h>
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#include <elog.h>
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@ -35,6 +34,8 @@
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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#include "chip.h"
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void __weak mainboard_romstage_entry(int s3_resume)
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{
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/* By default, don't do anything */
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@ -14,7 +14,6 @@
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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@ -23,6 +22,8 @@
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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static void pci_domain_set_resources(struct device *dev)
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{
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printk(BIOS_SPEW, "%s/%s (%s)\n",
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#ifndef _SOC_RAMSTAGE_H_
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#define _SOC_RAMSTAGE_H_
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#include <chip.h>
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#include <device/device.h>
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#include <fsp/ramstage.h>
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#include "../../chip.h"
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#define V_PCH_LPC_RID_A0 0x00 // A0 Stepping
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#define V_PCH_LPC_RID_A1 0x04 // A1 Stepping
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#define V_PCH_LPC_RID_A2 0x08 // A2 Stepping
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <arch/cbfs.h>
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#include <chip.h>
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#include <cpu/x86/mtrr.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <build.h>
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#include <pc80/mc146818rtc.h>
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#include "../chip.h"
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void program_base_addresses(void)
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{
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uint32_t reg;
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <wrdd.h>
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#include "chip.h"
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/*
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* List of supported C-states in this processor.
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*/
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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#if CONFIG(HAVE_ACPI_TABLES)
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const char *soc_acpi_name(const struct device *dev)
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{
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <chip.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/common/common.h>
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#include "chip.h"
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/ramstage.h>
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#include <string.h>
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#include "chip.h"
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static const int serial_io_dev[] = {
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PCH_DEVFN_I2C0,
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PCH_DEVFN_I2C1,
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#ifndef _SOC_RAMSTAGE_H_
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#define _SOC_RAMSTAGE_H_
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#include <chip.h>
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#include <device/device.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include "../../chip.h"
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void mainboard_silicon_init_params(FSP_S_CONFIG *params);
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void soc_init_pre_device(void *chip_info);
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#include <arch/ebda.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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void smm_region(void **start, size_t *size)
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{
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*start = (void *)sa_get_tseg_base();
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*/
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include "chip.h"
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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*/
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#include <assert.h>
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#include <chip.h>
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#include <cpu/x86/msr.h>
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#include <console/console.h>
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#include <fsp/util.h>
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#include <soc/romstage.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "../chip.h"
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static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
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{
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unsigned int i;
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <cpu/x86/mtrr.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <string.h>
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#include <timestamp.h>
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#include "../chip.h"
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#define FSP_SMBIOS_MEMORY_INFO_GUID \
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{ \
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0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <intelblocks/fast_spi.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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#define CSME0_FBE 0xf
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#define CSME0_BAR 0x0
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#define CSME0_FID 0xb0
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#include <soc/pattrs.h>
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#include <soc/pci_devs.h>
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#include <soc/broadwell_de.h>
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#include <chip.h>
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#include <version.h>
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#include "chip.h"
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uint16_t get_pmbase(void)
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{
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return ACPI_BASE_ADDRESS;
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <chip.h>
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#include "chip.h"
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static void pci_domain_set_resources(struct device *dev)
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{
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#include <drivers/intel/fsp1_0/fsp_util.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <chip.h>
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#include <fsp.h>
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#include "../chip.h"
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/* Copy the default UPD region and settings to a buffer for modification */
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static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
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{
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <chip.h>
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#include "chip.h"
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typedef struct soc_intel_fsp_broadwell_de_config config_t;
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#include <device/mmio.h>
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pmclib.h>
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#include <vendorcode/google/chromeos/gnvs.h>
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#include <wrdd.h>
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#include "chip.h"
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/*
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* List of supported C-states in this processor.
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*/
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include "chip.h"
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#if CONFIG(HAVE_ACPI_TABLES)
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const char *soc_acpi_name(const struct device *dev)
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{
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <chip.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "chip.h"
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static void soc_fsp_load(void)
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{
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fsps_load(romstage_handoff_is_resume());
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <console/post_codes.h>
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#include <cpu/x86/smm.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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#define CAMERA1_CLK 0x8000 /* Camera 1 Clock */
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#define CAMERA2_CLK 0x8080 /* Camera 2 Clock */
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#define CAM_CLK_EN (1 << 1)
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#ifndef _SOC_RAMSTAGE_H_
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#define _SOC_RAMSTAGE_H_
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#include <chip.h>
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#include <device/device.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include "../../chip.h"
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void mainboard_silicon_init_params(FSP_S_CONFIG *params);
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void soc_init_pre_device(void *chip_info);
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#include <arch/ebda.h>
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#include <cbmem.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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#include "chip.h"
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void smm_region(void **start, size_t *size)
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{
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*start = (void *)sa_get_tseg_base();
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*/
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#include <bootstate.h>
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#include <chip.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/device.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include "chip.h"
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/*
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* Set which power state system will be after reapplying
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* the power (from G3 State)
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@ -13,7 +13,6 @@
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <cpu/x86/mtrr.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <string.h>
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#include <timestamp.h>
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|
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#include "../chip.h"
|
||||
|
||||
#define FSP_SMBIOS_MEMORY_INFO_GUID \
|
||||
{ \
|
||||
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <intelblocks/fast_spi.h>
|
||||
|
@ -25,6 +24,8 @@
|
|||
#include <soc/pcr_ids.h>
|
||||
#include <soc/pm.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#define CSME0_FBE 0xf
|
||||
#define CSME0_BAR 0x0
|
||||
#define CSME0_FID 0xb0
|
||||
|
|
|
@ -18,11 +18,12 @@
|
|||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <arch/cpu.h>
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <soc/QuarkNcSocId.h>
|
||||
|
||||
#include "../../chip.h"
|
||||
|
||||
void mainboard_gpio_i2c_init(struct device *dev);
|
||||
asmlinkage void chipset_teardown_car(void);
|
||||
|
||||
|
|
|
@ -21,7 +21,6 @@
|
|||
#include <arch/ioapic.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <cbmem.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
@ -51,6 +50,8 @@
|
|||
#include <wrdd.h>
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/*
|
||||
* List of suported C-states in this processor.
|
||||
*/
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <device/pci_ops.h>
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <intelblocks/cse.h>
|
||||
|
@ -37,6 +36,8 @@
|
|||
#include <soc/pmc.h>
|
||||
#include <soc/smbus.h>
|
||||
|
||||
#include "../chip.h"
|
||||
|
||||
#define PCR_DMI_DMICTL 0x2234
|
||||
#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
|
||||
#define PCR_DMI_ACPIBA 0x27B4
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
@ -33,6 +32,8 @@
|
|||
#include <soc/ramstage.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
void soc_init_pre_device(void *chip_info)
|
||||
{
|
||||
/* Snapshot the current GPIO IRQ polarities. FSP is setting a
|
||||
|
|
|
@ -13,7 +13,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <chip.h>
|
||||
#include <bootmode.h>
|
||||
#include <bootstate.h>
|
||||
#include <device/pci.h>
|
||||
|
@ -42,6 +41,8 @@
|
|||
#include <soc/systemagent.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
struct pcie_entry {
|
||||
unsigned int devfn;
|
||||
unsigned int func_count;
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <chip.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
|
@ -46,6 +45,8 @@
|
|||
#include <soc/systemagent.h>
|
||||
#include <timer.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
|
||||
static const u8 power_limit_time_sec_to_msr[] = {
|
||||
[0] = 0x00,
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <bootstate.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <console/post_codes.h>
|
||||
#include <cpu/x86/mp.h>
|
||||
|
@ -41,6 +40,8 @@
|
|||
#include <stdlib.h>
|
||||
#include <timer.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#define PSF_BASE_ADDRESS 0xA00
|
||||
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
|
||||
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
|
||||
|
|
|
@ -17,11 +17,12 @@
|
|||
#ifndef _SOC_RAMSTAGE_H_
|
||||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <fsp/ramstage.h>
|
||||
#include <fsp/soc_binding.h>
|
||||
|
||||
#include "../../../chip.h"
|
||||
|
||||
#define FSP_SIL_UPD SILICON_INIT_UPD
|
||||
#define FSP_MEM_UPD MEMORY_INIT_UPD
|
||||
|
||||
|
|
|
@ -17,11 +17,12 @@
|
|||
#ifndef _SOC_RAMSTAGE_H_
|
||||
#define _SOC_RAMSTAGE_H_
|
||||
|
||||
#include <chip.h>
|
||||
#include <device/device.h>
|
||||
#include <fsp/api.h>
|
||||
#include <fsp/util.h>
|
||||
|
||||
#include "../../../chip.h"
|
||||
|
||||
#define FSP_SIL_UPD FSP_S_CONFIG
|
||||
#define FSP_MEM_UPD FSP_M_CONFIG
|
||||
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
#include <arch/ebda.h>
|
||||
#include <device/mmio.h>
|
||||
#include <cbmem.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
@ -29,6 +28,8 @@
|
|||
#include <soc/systemagent.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
size_t mmap_region_granularity(void)
|
||||
{
|
||||
if (CONFIG(HAVE_SMI_HANDLER))
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <chip.h>
|
||||
#include <console/streams.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
|
@ -25,6 +24,8 @@
|
|||
#include <soc/pei_data.h>
|
||||
#include <soc/pei_wrapper.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
static void ABI_X86 send_to_console(unsigned char b)
|
||||
{
|
||||
console_tx_byte(b);
|
||||
|
|
|
@ -16,7 +16,6 @@
|
|||
*/
|
||||
|
||||
#include <bootstate.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/mmio.h>
|
||||
#include <device/device.h>
|
||||
|
@ -28,6 +27,8 @@
|
|||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
void pmc_set_disb(void)
|
||||
{
|
||||
/* Set the DISB after DRAM init */
|
||||
|
|
|
@ -17,7 +17,6 @@
|
|||
#include <arch/cbfs.h>
|
||||
#include <arch/early_variables.h>
|
||||
#include <assert.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/mtrr.h>
|
||||
#include <device/device.h>
|
||||
|
@ -37,6 +36,8 @@
|
|||
#include <stdint.h>
|
||||
#include <vendorcode/google/chromeos/chromeos.h>
|
||||
|
||||
#include "../chip.h"
|
||||
|
||||
/* SOC initialization before RAM is enabled */
|
||||
void soc_pre_ram_init(struct romstage_params *params)
|
||||
{
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
#include <cpu/x86/mtrr.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cbmem.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <fsp/util.h>
|
||||
|
@ -37,6 +36,8 @@
|
|||
#include <timestamp.h>
|
||||
#include <security/vboot/vboot_common.h>
|
||||
|
||||
#include "../chip.h"
|
||||
|
||||
#define FSP_SMBIOS_MEMORY_INFO_GUID \
|
||||
{ \
|
||||
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <chip.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
|
@ -23,6 +22,8 @@
|
|||
#include <soc/pci_devs.h>
|
||||
#include <soc/thermal.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#define MAX_TRIP_TEMP 205
|
||||
#define DEFAULT_TRIP_TEMP 50
|
||||
|
||||
|
|
Loading…
Reference in New Issue