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AMD northbridges: factor out CPU allocation 

Factor CPU allocation out of AMD northbridge codes. As CPU topology
information is required for generation of certain ACPI tables, make
this code globally available.

For AMDK8 and AMDFAM10 northbridge, there is a possible case of
BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from
devicetree unused, so always use that node for BSP CPU.

Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1418
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki 2012-08-07 17:12:11 +03:00 committed by Alexandru Gagniuc
parent cd9fc1aa5f
commit c33f1e9261
10 changed files with 122 additions and 118 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/devices/Makefile.inc
View File

@ -1,5 +1,6 @@
ramstage-y += device.c
ramstage-y += root_device.c
ramstage-y += cpu_device.c
ramstage-y += device_util.c
ramstage-y += pci_device.c
ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c

71
src/devices/cpu_device.c Normal file
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@ -0,0 +1,71 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
void remap_bsp_lapic(struct bus *cpu_bus)
{
struct device_path cpu_path;
device_t cpu;
u32 bsp_lapic_id = lapicid();
if (bsp_lapic_id) {
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = 0;
cpu = find_dev_path(cpu_bus, &cpu_path);
if (cpu)
cpu->path.apic.apic_id = bsp_lapic_id;
}
}
device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled)
{
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id;
/* Update CPU in devicetree. */
if (enabled)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
return NULL;
cpu->enabled = enabled;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
return cpu;
}
void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread)
{
cpu->path.apic.node_id = node;
cpu->path.apic.package_id = package;
cpu->path.apic.core_id = core;
cpu->path.apic.thread_id = thread;
}

10
src/include/device/device.h
View File

@ -155,6 +155,16 @@ device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
device_t dev_find_lapic(unsigned apic_id);
int dev_count_cpu(void);
void remap_bsp_lapic(struct bus *cpu_bus);
device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled);
void set_cpu_topology(device_t cpu, unsigned node, unsigned package, unsigned core, unsigned thread);
#define amd_cpu_topology(cpu, node, core) \
set_cpu_topology(cpu, node, 0, core, 0)
#define intel_cpu_topology(cpu, package, core, thread) \
set_cpu_topology(cpu, 0, package, core, thread)
/* Debug functions */
void print_resource_tree(struct device * root, int debug_level,
const char *msg);

2
src/include/device/path.h
View File

@ -39,8 +39,10 @@ struct i2c_path
struct apic_path
{
unsigned apic_id;
unsigned package_id;
unsigned node_id;
unsigned core_id;
unsigned thread_id;
};
struct ioapic_path

23
src/northbridge/amd/agesa/family10/northbridge.c
View File

@ -1374,11 +1374,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
u32 lapicid_start = 0;
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
/*
* APIC ID calucation is tightly coupled with AGESA v5 code.
* This calculation MUST match the assignment calculation done
@ -1394,22 +1390,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
if (nodes * (cores_found + 1) >= 0x10) {
lapicid_start = 0x10;
}
cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j);
/* Update CPU in devicetree. */
if (enable_node)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
continue;
cpu->enabled = enable_node;
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (cores_found + 1)) : j);
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
return max;

17
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -831,6 +831,7 @@ static void cpu_bus_set_resources(device_t dev) {
static u32 cpu_bus_scan(device_t dev, u32 max)
{
struct bus *cpu_bus = dev->link_list;
device_t cpu;
int apic_id, cores_found;
@ -842,20 +843,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
cores_found = (pci_read_config32(dev_find_slot(0,PCI_DEVFN(0x18,0x3)), 0xe8) >> 12) & 3;
printk(BIOS_DEBUG, " AP siblings=%d\n", cores_found);
for (apic_id = 0; apic_id <= cores_found; apic_id++) {
struct device_path cpu_path;
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id;
cpu = alloc_find_dev(dev->link_list, &cpu_path);
if (!cpu)
continue;
cpu->enabled = 1;
cpu->path.apic.node_id = 0;
cpu->path.apic.core_id = apic_id;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
cpu = add_cpu_device(cpu_bus, apic_id, 1);
if (cpu)
amd_cpu_topology(cpu, 0, apic_id);
}
return max;
}

24
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -1052,11 +1052,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
u32 lapicid_start = 0;
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
/*
* APIC ID calucation is tightly coupled with AGESA v5 code.
* This calculation MUST match the assignment calculation done
@ -1078,23 +1074,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}
cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, cpu_path.apic.apic_id);
i, j, apic_id);
/* Update CPU in devicetree. */
if (enable_node)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
continue;
cpu->enabled = enable_node;
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
return max;

24
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -1060,11 +1060,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
u32 lapicid_start = 0;
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
/*
* APIC ID calucation is tightly coupled with AGESA v5 code.
* This calculation MUST match the assignment calculation done
@ -1086,23 +1082,13 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}
cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, cpu_path.apic.apic_id);
i, j, apic_id);
/* Update CPU in devicetree. */
if (enable_node)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
continue;
cpu->enabled = enable_node;
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
return max;

32
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -1344,6 +1344,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
#endif
/* Find which cpus are present */
cpu_bus = dev->link_list;
/* Always use the devicetree node with lapic_id 0 for BSP. */
remap_bsp_lapic(cpu_bus);
for(i = 0; i < nodes; i++) {
device_t cdb_dev;
unsigned busn, devn;
@ -1406,34 +1410,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
}
for (j = 0; j <=jj; j++ ) {
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
/* Update CPU in devicetree. */
if (enable_node)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
continue;
u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ?
#if CONFIG_ENABLE_APIC_EXT_ID && (CONFIG_APIC_ID_OFFSET>0)
if(sysconf.enabled_apic_ext_id) {
if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) {
cpu->path.apic.apic_id += sysconf.apicid_offset;
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
apic_id += sysconf.apicid_offset;
}
}
#endif
cpu->enabled = enable_node;
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
return max;

36
src/northbridge/amd/amdk8/northbridge.c
View File

@ -1238,6 +1238,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
/* Find which cpus are present */
cpu_bus = dev->link_list;
/* Always use the devicetree node with lapic_id 0 for BSP. */
remap_bsp_lapic(cpu_bus);
for(i = 0; i < sysconf.nodes; i++) {
device_t cpu_dev;
@ -1306,38 +1310,18 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
{
jj = siblings;
}
#if 0
jj = 0; // if create cpu core1 path in amd_siblings by core0
#endif
for (j = 0; j <=jj; j++ ) {
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
/* Update CPU in devicetree. */
if (enable_node)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
continue;
u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
if(sysconf.enabled_apic_ext_id) {
if (cpu->path.apic.apic_id != 0 || sysconf.lift_bsp_apicid) {
cpu->path.apic.apic_id += sysconf.apicid_offset;
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
apic_id += sysconf.apicid_offset;
}
}
cpu->enabled = enable_node;
cpu->path.apic.node_id = i;
cpu->path.apic.core_id = j;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
if (cpu)
amd_cpu_topology(cpu, i, j);
} //j
}
return max;