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rush: Add gpio config for PWR button and LID open switch 

Due to CL https://chromium-review.googlesource.com/231250,
depthcharge now detects gpio state based on gpio configurations
done by coreboot instead of redoing configuration at
depthcharge. However, PWR button and LID open pins have not
been configured in coreboot. So, add the missing code here.
Otherwise, TOT coreboot/depthcharge rush build can not load
in kernel.

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build rush and test with pwr button press and lid switch

Change-Id: I7acc5e021fa769f68d4cbfd7202df325d4ea73c2
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a25dff24a2dcd33fcd15eb766432414af215c3ab
Original-Change-Id: I6c322cd987967920f236aae653294db079678408
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233322
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Jimmy Zhang 2014-12-04 17:24:43 -08:00 committed by Patrick Georgi
parent 36fd82dfc4
commit c355826e21
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/google/rush/bootblock.c
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@ -50,6 +50,12 @@ static const struct pad_config padcfgs[] = {
PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE), PAD_CFG_GPIO_INPUT(GPIO_X1_AUD, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE), PAD_CFG_GPIO_INPUT(KB_ROW17, PINMUX_PULL_NONE),
PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE), PAD_CFG_GPIO_INPUT(KB_COL3, PINMUX_PULL_NONE),
/* Power Button */
PAD_CFG_GPIO_INPUT(KB_COL0, PINMUX_PULL_NONE),
/* Lid Open Switch */
PAD_CFG_GPIO_INPUT(KB_ROW4, PINMUX_PULL_UP),
}; };
static const struct pad_config i2cpad[] = { static const struct pad_config i2cpad[] = {