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mb/google/zork: Enable psp_verstage 

Finally enable psp_verstage for zork.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Martin Roth 2020-06-14 17:26:14 -06:00 committed by Martin Roth
parent f38af663d2
commit c35d4fa377
1 changed files with 32 additions and 2 deletions
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34
src/mainboard/google/zork/Kconfig
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@ -100,8 +100,6 @@ config ONBOARD_VGA_IS_PRIMARY
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_LID_SWITCH
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_SEPARATE_VERSTAGE
config VBOOT_VBNV_OFFSET
hex
@ -123,6 +121,22 @@ config DRIVER_TPM_I2C_ADDR
hex
default 0x50
config PICASSO_FW_A_POSITION
hex
default 0xFF031040
depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
help
Location of the AMD firmware in the RW_A region. This is the
start of the RW-A region + 64 bytes for the cbfs header.
config PICASSO_FW_B_POSITION
hex
default 0xFF3CF040
depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
help
Location of the AMD firmware in the RW_B region. This is the
start of the RW-A region + 64 bytes for the cbfs header.
config VARIANT_HAS_FW_CONFIG
bool
help
@ -151,4 +165,20 @@ config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW
default 2 if BOARD_GOOGLE_VILBOZ
default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS
config VBOOT_STARTS_BEFORE_BOOTBLOCK
bool "PSP verstage"
default y if VBOOT
help
Firmware verification happens before the main processor is brought
online.
config VBOOT_STARTS_IN_BOOTBLOCK
bool "X86 verstage (in bootblock)"
depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK
select VBOOT_SEPARATE_VERSTAGE
help
Firmware verification happens during the end of or right after the
bootblock. This implies that a static VBOOT2_WORK() buffer must be
allocated in memlayout.
endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ