mb/google/zork: Enable psp_verstage
Finally enable psp_verstage for zork. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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@ -100,8 +100,6 @@ config ONBOARD_VGA_IS_PRIMARY
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_SEPARATE_VERSTAGE
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config VBOOT_VBNV_OFFSET
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hex
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@ -123,6 +121,22 @@ config DRIVER_TPM_I2C_ADDR
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hex
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default 0x50
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config PICASSO_FW_A_POSITION
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hex
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default 0xFF031040
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depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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Location of the AMD firmware in the RW_A region. This is the
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start of the RW-A region + 64 bytes for the cbfs header.
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config PICASSO_FW_B_POSITION
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hex
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default 0xFF3CF040
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depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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Location of the AMD firmware in the RW_B region. This is the
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start of the RW-A region + 64 bytes for the cbfs header.
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config VARIANT_HAS_FW_CONFIG
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bool
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help
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@ -151,4 +165,20 @@ config VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW
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default 2 if BOARD_GOOGLE_VILBOZ
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default VARIANT_MIN_BOARD_ID_V3_SCHEMATICS
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config VBOOT_STARTS_BEFORE_BOOTBLOCK
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bool "PSP verstage"
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default y if VBOOT
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help
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Firmware verification happens before the main processor is brought
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online.
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config VBOOT_STARTS_IN_BOOTBLOCK
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bool "X86 verstage (in bootblock)"
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depends on VBOOT && ! VBOOT_STARTS_BEFORE_BOOTBLOCK
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select VBOOT_SEPARATE_VERSTAGE
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help
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Firmware verification happens during the end of or right after the
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bootblock. This implies that a static VBOOT2_WORK() buffer must be
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allocated in memlayout.
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endif # BOARD_GOOGLE_BASEBOARD_TREMBYLE || BOARD_GOOGLE_BASEBOARD_DALBOZ
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