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added cache initialization code 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2004-04-21 22:30:47 +00:00
parent 12c3154cee
commit c36b4275c6
1 changed files with 15 additions and 0 deletions
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15
src/arch/ppc/init/crt0.S.lb
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@ -32,6 +32,21 @@ system_reset:
#if USE_DCACHE_RAM == 1 #if USE_DCACHE_RAM == 1
#define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1) #define DCACHE_RAM_END (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - 1)
/*
* Initialize data cache blocks
* (assumes cache block size of 32 bytes)
*
* NOTE: This may need to be moved to FAMILY_INIT if
* dcbz is not supported on all CPU's
*/
lis r1, DCACHE_RAM_BASE@h
ori r1, r1, DCACHE_RAM_BASE@l
li r3, (DCACHE_RAM_SIZE / 32)
mtctr r3
0: dcbz r0, r1
addi r1, r1, 32
bdnz 0b
/* /*
* Set up stack in cache. The SP must be 16-byte (4-word) aligned * Set up stack in cache. The SP must be 16-byte (4-word) aligned
* for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make * for SYSV EABI or 8-byte (2-word) aligned for PPC EABI, so we make