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Broadwell: Synchronize RO, Link Arbiter, and OBFF with FRC 

OBFF: Disable it by clearing bit fields in that W/O register.
RO: Enable Relaxed Ordering from each enabled Root Port.
Linker Arbiter: Set it to recommended setting.

BUG=None
TEST=Build an image and check the setting are applied correctly on
Samus.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>

Change-Id: I7a72217729d6f6ff5320738245c380c887c5912f
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 465b0a37c381930a4f0d74cd4fd69503a082911b
Original-Change-Id: I284e9eba1c2fceb690d3ef48b45a6f36d07ff84c
Original-Reviewed-on: https://chromium-review.googlesource.com/219993
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com>
Original-Tested-by: Kenji Chen <kenji.chen@intel.com>
Reviewed-on: http://review.coreboot.org/9210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Kenji Chen 2014-09-26 02:48:16 +08:00 committed by Patrick Georgi
parent 8ef55ee996
commit c373f503db
1 changed files with 7 additions and 2 deletions
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9
src/soc/intel/broadwell/pcie.c
View File

@ -523,8 +523,8 @@ static void pch_pcie_early(struct device *dev)
pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); pcie_update_cfg(dev, 0x338, ~(1 << 26), 0);
} }
/* Enable LTR in Root Port. */ /* Enable LTR in Root Port. Disable OBFF. */
pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10));
pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
@ -550,6 +550,11 @@ static void pch_pcie_early(struct device *dev)
/* Set Extended Capability to offset 200h and Advanced Error Report. */ /* Set Extended Capability to offset 200h and Advanced Error Report. */
pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001);
pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6),
(1 << 20) | (3 << 6));
/* Enable Relaxed Order from Root Port. */
pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23));
if (rp == 1 || rp == 5 || rp == 6) if (rp == 1 || rp == 5 || rp == 6)
pcie_update_cfg8(dev, 0xf7, ~0xc, 0); pcie_update_cfg8(dev, 0xf7, ~0xc, 0);