From c3892c8fa8defc7bc898c1a1ba8d733c759b944a Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Fri, 23 Feb 2018 10:11:27 +0800 Subject: [PATCH] skylake: Fix unwanted disablement of ACPI UPWE In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS. This change is inspired by xhci_port_state_to_neutral in linux driver. It will mask all RO and RWS bits and set WDE and WCE. BUG=b:70777816 TEST=System won't be awakend from s3 automatically when usb devices is attached. Also system can be awakend by hotplugging usb devices under S3. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen Reviewed-on: https://review.coreboot.org/23848 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/skylake/acpi/xhci.asl | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 08f35bcf28..29367de6dd 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -29,14 +29,20 @@ Method (UPWE, 3, Serialized) /* Map ((XMEM << 16) + Local0 in PSCR */ OperationRegion (PSCR, SystemMemory, Add (ShiftLeft (Arg2, 16), Local0), 0x10) - Field (PSCR, AnyAcc, NoLock, Preserve) + Field (PSCR, DWordAcc, NoLock, Preserve) { - , 25, - UPCE, 1, - UPDE, 1, + PSCT, 32, } - Store (One, UPCE) - Store (One, UPDE) + Store(PSCT, Local0) + /* + * And port status/control reg with RO and RWS bits + * RO bits: 0, 2:3, 10:13, 24, 28:30 + * RWS bits: 5:9, 14:16, 25:27 + */ + And (Local0, ~0x80FE0012, Local0) + /* Set WCE and WDE bits */ + Or (Local0, 0x6000000, Local0) + Store(Local0, PSCT) } /*