diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
index 6fd6332eec..e72c61ce03 100644
--- a/src/cpu/amd/pi/00730F01/Kconfig
+++ b/src/cpu/amd/pi/00730F01/Kconfig
@@ -5,3 +5,11 @@ config CPU_AMD_PI_00730F01
 	select X86_AMD_FIXED_MTRRS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select MICROCODE_BLOB_UNDISCLOSED
+
+if CPU_AMD_PI_00730F01
+
+config ACPI_CPU_STRING
+	string
+	default "\\_SB.P%03d"
+
+endif # CPU_AMD_PI_00730F01
diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl
deleted file mode 100644
index ede5021e03..0000000000
--- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * Processor Object
- *
- */
-Scope (\_SB) {	/* define processor scope */
-
-	Device (P000) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 0)
-	}
-
-	Device (P001) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 1)
-	}
-
-	Device (P002) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 2)
-	}
-
-	Device (P003) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 3)
-	}
-
-	Device (P004) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 4)
-	}
-
-	Device (P005) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 5)
-	}
-
-	Device (P006) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 6)
-	}
-
-	Device (P007) {
-	Name(_HID, "ACPI0007")
-	Name(_UID, 7)
-	}
-} /* End _SB scope */
diff --git a/src/mainboard/pcengines/apu2/dsdt.asl b/src/mainboard/pcengines/apu2/dsdt.asl
index 61edb10485..789be13280 100644
--- a/src/mainboard/pcengines/apu2/dsdt.asl
+++ b/src/mainboard/pcengines/apu2/dsdt.asl
@@ -22,9 +22,6 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
-	/* Describe the processor tree (\_SB) */
-	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
-
 	/* Contains the supported sleep states for this chipset */
 	#include <southbridge/amd/common/acpi/sleepstates.asl>
 
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 46610c51e2..355820a815 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -869,10 +869,25 @@ void mp_init_cpus(struct bus *cpu_bus)
 			    MTRR_TYPE_WRPROT);
 }
 
+void generate_cpu_entries(const struct device *device)
+{
+	int cpu;
+	const int cores = get_cpu_count();
+
+	printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
+
+	/* Generate \_SB.Pxxx */
+	for (cpu = 0; cpu < cores; cpu++) {
+		acpigen_write_processor_device(cpu);
+		acpigen_write_processor_device_end();
+	}
+}
+
 static struct device_operations cpu_bus_ops = {
-	.read_resources	  = noop_read_resources,
-	.set_resources	  = noop_set_resources,
-	.init		  = mp_cpu_bus_init,
+	.read_resources	= noop_read_resources,
+	.set_resources	= noop_set_resources,
+	.init		= mp_cpu_bus_init,
+	.acpi_fill_ssdt	= generate_cpu_entries,
 };
 
 static void root_complex_enable_dev(struct device *dev)