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cpu,nb/amd/pi/00730F01: dynamically generate CPU devices 

Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.

TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Felix Held 2023-02-16 19:38:49 +01:00
parent 0a2c9d7913
commit c391bff443
4 changed files with 26 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/amd/pi/00730F01/Kconfig
View File

@ -5,3 +5,11 @@ config CPU_AMD_PI_00730F01
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select MICROCODE_BLOB_UNDISCLOSED select MICROCODE_BLOB_UNDISCLOSED
if CPU_AMD_PI_00730F01
config ACPI_CPU_STRING
string
default "\\_SB.P%03d"
endif # CPU_AMD_PI_00730F01

48
src/cpu/amd/pi/00730F01/acpi/cpu.asl
View File

@ -1,48 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}
Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}
Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}
Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}
Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}
Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}
Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}
Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */

3
src/mainboard/pcengines/apu2/dsdt.asl
View File

@ -22,9 +22,6 @@ DefinitionBlock (
/* PCI IRQ mapping for the Southbridge */ /* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/pi/hudson/acpi/pcie.asl> #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
/* Describe the processor tree (\_SB) */
#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
/* Contains the supported sleep states for this chipset */ /* Contains the supported sleep states for this chipset */
#include <southbridge/amd/common/acpi/sleepstates.asl> #include <southbridge/amd/common/acpi/sleepstates.asl>

21
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -869,10 +869,25 @@ void mp_init_cpus(struct bus *cpu_bus)
MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
} }
void generate_cpu_entries(const struct device *device)
{
int cpu;
const int cores = get_cpu_count();
printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores);
/* Generate \_SB.Pxxx */
for (cpu = 0; cpu < cores; cpu++) {
acpigen_write_processor_device(cpu);
acpigen_write_processor_device_end();
}
}
static struct device_operations cpu_bus_ops = { static struct device_operations cpu_bus_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.init = mp_cpu_bus_init, .init = mp_cpu_bus_init,
.acpi_fill_ssdt = generate_cpu_entries,
}; };
static void root_complex_enable_dev(struct device *dev) static void root_complex_enable_dev(struct device *dev)