diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index c9d7da6cbc..c5207f205f 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/alderlake
 	# Enable CNVi BT
 	register "CnviBtCore" = "true"
 
+	# Sagv Configuration
+	register "SaGv" = "SaGv_Enabled"
+
 	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC3)"		# Type-C Port3