From c398a204b40f6a9ccb06cb9b6af67ad528638a05 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Wed, 19 May 2021 09:42:23 +0530 Subject: [PATCH] mb/intel/adlrvp: Enable SaGv support BUG=b:187446498 TEST=Boot and verify memory trains at all the SaGv points through FSP debug logs. Signed-off-by: V Sowmya Change-Id: I883ae50b07e7b1d5554763fd79079d40b264b721 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54647 Tested-by: build bot (Jenkins) Reviewed-by: Balaji Manigandan Reviewed-by: Subrata Banik --- src/mainboard/intel/adlrvp/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index c9d7da6cbc..c5207f205f 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/alderlake # Enable CNVi BT register "CnviBtCore" = "true" + # Sagv Configuration + register "SaGv" = "SaGv_Enabled" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3