From c3a9e5371453c9ce713ce6625105bde66ff28d76 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 30 Sep 2021 20:46:15 +0200 Subject: [PATCH] mb/google/guybrush/bootblock: add comment to PM_ACPI_CONF write Document what setting the PM_ACPI_S5_LPC_PIN_MODE and PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will eventually be factored out and moved to the Cezanne SoC code. Signed-off-by: Felix Held Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/google/guybrush/bootblock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c index 3f7d5a1bf5..9c9fce7e8d 100644 --- a/src/mainboard/google/guybrush/bootblock.c +++ b/src/mainboard/google/guybrush/bootblock.c @@ -61,6 +61,7 @@ void bootblock_mainboard_early_init(void) dword |= PM_ESPI_CS_USE_DATA2; pm_write32(PM_SPI_PAD_PU_PD, dword); + /* Switch the pads that can be used as either LPC or secondary eSPI to 1.8V mode */ dword = pm_read32(PM_ACPI_CONF); dword |= PM_ACPI_S5_LPC_PIN_MODE | PM_ACPI_S5_LPC_PIN_MODE_SEL; pm_write32(PM_ACPI_CONF, dword);