soc/intel/cannonlake: Read HPR_CAUSE0 register

Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on
newer platforms.

Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/cannonlake/include/soc/pm.h

@@ -143,6 +143,7 @@ struct chipset_power_state {
 	uint32_t gen_pmcon_a;
 	uint32_t gen_pmcon_b;
 	uint32_t gblrst_cause[2];
+	uint32_t hpr_cause0;
 	uint32_t prev_sleep_state;
 } __packed;
 

src/soc/intel/cannonlake/include/soc/pmc.h

@@ -142,6 +142,7 @@ extern struct device_operations pmc_ops;
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)
 #define GBLRST_CAUSE1			0x1928
+#define HPR_CAUSE0			0x192C
 
 #define LTR_IGN				0x1B0C
 #define   IGN_GBE			(1 << 3)

src/soc/intel/cannonlake/pmutil.c

@@ -232,12 +232,15 @@ void soc_fill_power_state(struct chipset_power_state *ps)
 	ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B);
 	ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0);
 	ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1);
+	ps->hpr_cause0 = read32(pmc + HPR_CAUSE0);
 
 	printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n",
 		ps->gen_pmcon_a, ps->gen_pmcon_b);
 
 	printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n",
 		ps->gblrst_cause[0], ps->gblrst_cause[1]);
+
+	printk(BIOS_DEBUG, "HPR_CAUSE0: %08x\n", ps->hpr_cause0);
 }
 
 /* STM Support */