use CONFIG_LB_MEM_TOPK instead 1M hardcode from issue 50
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -3,54 +3,58 @@
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static inline __attribute__((always_inline)) void clear_1m_ram(void)
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{
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__asm__ volatile (
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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);
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 1), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRCOMB), %eax\n\t"
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"wrmsr\n\t"
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__asm__ volatile (
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"wrmsr"
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: /* No outputs */
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: "c" (0x200), "a" (0 | MTRR_TYPE_WRCOMB), "d" (0)
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);
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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__asm__ volatile (
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"wrmsr"
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: /* No outputs */
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: "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
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);
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__asm__ volatile(
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/* clear the first 1M */
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"movl $0x0, %edi\n\t"
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"cld\n\t"
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"movl $(0x100000>>2), %ecx\n\t"
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"xorl %eax, %eax\n\t"
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"rep stosl\n\t"
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:
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: "a"(0), "D"(0) ,"c" ((CONFIG_LB_MEM_TOPK<<10)>>2)
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);
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__asm__ volatile (
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/* disable cache */
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"movl %cr0, %eax\n\t"
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"orl $(0x1<<30),%eax\n\t"
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"movl %eax, %cr0\n\t"
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);
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/* enable caching for first 1M using variable mtrr */
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"movl $0x200, %ecx\n\t"
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"xorl %edx, %edx\n\t"
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"movl $(0 | 6), %eax\n\t"
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// "movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
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"wrmsr\n\t"
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"movl $0x201, %ecx\n\t"
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"movl $0x0000000f, %edx\n\t"
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"movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax\n\t"
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"wrmsr\n\t"
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__asm__ volatile (
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"wrmsr"
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: /* No outputs */
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: "c" (0x200), "a" (0 | MTRR_TYPE_WRBACK), "d" (0)
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);
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__asm__ volatile (
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"wrmsr"
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: /* No outputs */
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: "c" (0x201), "a" ((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), "d" (0x0000000f)
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);
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__asm__ volatile (
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/* enable cache */
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"movl %cr0, %eax\n\t"
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"andl $0x9fffffff,%eax\n\t"
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"movl %eax, %cr0\n\t"
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"invd\n\t"
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);
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}
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