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soc/intel/baytrail/sata.c: Fix SATA init sequence 

SeaBIOS on Bay Trail would time out when trying to access a SATA drive.
Turns out that there's two mistakes in the SATA initialization sequence:

 - PCI register 0x94 is wrongly cleared with a bitwise-and operation.
 - PCI register 0x9c is instead written to 0x98, clobbering the latter.

After correcting them, SeaBIOS can boot from SATA on Asrock Q1900M.

Change-Id: I5cc4b9b1695653066f47de67afc79f08f0341cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-31 21:37:26 +02:00
parent e231949b78
commit c3be055fbe
1 changed files with 2 additions and 4 deletions
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6
src/soc/intel/baytrail/sata.c
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@ -128,14 +128,12 @@ static void sata_init(struct device *dev)
/* Enable clock for ports */ /* Enable clock for ports */
reg32 = pci_read_config32(dev, 0x94); reg32 = pci_read_config32(dev, 0x94);
reg32 |= 0x3f << 24; reg32 &= ~(config->sata_port_map << 24);
pci_write_config32(dev, 0x94, reg32);
reg32 &= (config->sata_port_map ^ 0x3) << 24;
pci_write_config32(dev, 0x94, reg32); pci_write_config32(dev, 0x94, reg32);
/* Lock SataGc register */ /* Lock SataGc register */
reg32 = (0x1 << 31) | (0x7 << 12); reg32 = (0x1 << 31) | (0x7 << 12);
pci_write_config32(dev, 0x98, reg32); pci_write_config32(dev, 0x9c, reg32);
} }
static void sata_enable(struct device *dev) static void sata_enable(struct device *dev)