ACPI: Replace smm_setup_structures()

Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/acpi/Kconfig

@@ -24,6 +24,9 @@ config ACPI_INTEL_HARDWARE_SLEEP_VALUES
 	  Provide common definitions for Intel hardware PM1_CNT register sleep
 	  values.
 
+config ACPI_NO_SMI_GNVS
+	bool
+
 config ACPI_NO_PCAT_8259
 	bool
 	help

src/arch/x86/acpi_s3.c

@@ -4,7 +4,6 @@
 #include <string.h>
 #include <acpi/acpi.h>
 #include <arch/cpu.h>
-#include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <cpu/x86/smm.h>
 #include <fallback.h>
@@ -79,16 +78,8 @@ void __weak mainboard_suspend_resume(void)
 
 void acpi_resume(void *wake_vec)
 {
-	if (CONFIG(HAVE_SMI_HANDLER)) {
-		void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
-
-		/* Restore GNVS pointer in SMM if found */
-		if (gnvs_address) {
-			printk(BIOS_DEBUG, "Restore GNVS pointer to %p\n",
-			       gnvs_address);
-			smm_setup_structures(gnvs_address, NULL, NULL);
-		}
-	}
+	/* Restore GNVS pointer in SMM if found. */
+	apm_control(APM_CNT_GNVS_UPDATE);
 
 	/* Call mainboard resume handler first, if defined. */
 	mainboard_suspend_resume();

src/cpu/amd/agesa/Kconfig

@@ -17,6 +17,7 @@ config CPU_AMD_AGESA
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_AGESA
 

src/cpu/amd/pi/Kconfig

@@ -17,6 +17,7 @@ config CPU_AMD_PI
 	select SPI_FLASH if HAVE_ACPI_RESUME
 	select SMM_ASEG
 	select SSE2
+	select ACPI_NO_SMI_GNVS
 
 if CPU_AMD_PI
 

src/cpu/x86/smm/smi_trigger.c

@@ -1,9 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi_gnvs.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 
+static void set_smm_gnvs_ptr(void);
+
 int apm_control(u8 cmd)
 {
 	if (!CONFIG(HAVE_SMI_HANDLER))
@@ -21,7 +24,8 @@ int apm_control(u8 cmd)
 		printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n");
 		break;
 	case APM_CNT_GNVS_UPDATE:
-		break;
+		set_smm_gnvs_ptr();
+		return 0;
 	case APM_CNT_FINALIZE:
 		printk(BIOS_DEBUG, "Finalizing SMM.\n");
 		break;
@@ -41,3 +45,32 @@ int apm_control(u8 cmd)
 	printk(BIOS_DEBUG, "APMC done.\n");
 	return 0;
 }
+
+static void set_smm_gnvs_ptr(void)
+{
+	uintptr_t gnvs_address;
+
+	if (CONFIG(ACPI_NO_SMI_GNVS)) {
+		printk(BIOS_WARNING, "%s() is not implemented\n", __func__);
+		return;
+	}
+
+	gnvs_address = (uintptr_t)acpi_get_gnvs();
+	if (!gnvs_address)
+		return;
+
+	/*
+	 * Issue SMI to set the gnvs pointer in SMM.
+	 *
+	 * EAX = APM_CNT_GNVS_UPDATE
+	 * EBX = gnvs pointer
+	 * EDX = APM_CNT
+	 */
+	asm volatile (
+		"outb %%al, %%dx\n\t"
+		: /* ignore result */
+		: "a" (APM_CNT_GNVS_UPDATE),
+		  "b" (gnvs_address),
+		  "d" (APM_CNT)
+	);
+}

src/include/cpu/x86/smm.h

@@ -48,8 +48,6 @@ void cpu_smi_handler(void);
 void northbridge_smi_handler(void);
 void southbridge_smi_handler(void);
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
-
 void mainboard_smi_gpi(u32 gpi_sts);
 int  mainboard_smi_apmc(u8 data);
 void mainboard_smi_sleep(u8 slp_typ);

src/soc/amd/picasso/Kconfig

@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDK_2017_BINDING
 	select HAVE_CF9_RESET
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select ACPI_NO_SMI_GNVS
 
 config MEMLAYOUT_LD_FILE
 	string

src/soc/amd/picasso/smi.c

@@ -11,11 +11,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/soc/amd/stoneyridge/Kconfig

@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
 	select HAVE_SMI_HANDLER
 	select SSE2
 	select RTC
+	select ACPI_NO_SMI_GNVS
 
 config AMD_APU_STONEYRIDGE
 	bool

src/soc/amd/stoneyridge/smi.c

@@ -10,11 +10,6 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/soc/intel/baytrail/smm.c

@@ -97,22 +97,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((uint32_t)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/baytrail/southcluster.c

@@ -494,7 +494,7 @@ static void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/braswell/acpi.c

@@ -512,7 +512,7 @@ void southcluster_inject_dsdt(const struct device *device)
 			gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT */
 		acpigen_write_scope("\\");

src/soc/intel/braswell/smm.c

@@ -99,22 +99,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((uint32_t)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/broadwell/lpc.c

@@ -584,7 +584,7 @@ static void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/broadwell/smi.c

@@ -86,22 +86,3 @@ static void __unused southbridge_clear_smi_status(void)
 	/* Set EOS bit so other SMIs can occur. */
 	enable_smi(EOS);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((u32)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/common/block/acpi/acpi.c

@@ -240,7 +240,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/common/block/smm/smm.c

@@ -70,22 +70,3 @@ void global_smi_enable_no_pwrbtn(void)
 {
 	smm_southbridge_enable(GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((u32)gnvs),
-		  "d" (APM_CNT)
-	);
-}

src/soc/intel/denverton_ns/acpi.c

@@ -292,7 +292,7 @@ void southcluster_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/denverton_ns/smm.c

@@ -56,19 +56,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile("outb %%al, %%dx\n\t"
-		     : /* ignore result */
-		     : "a"(APM_CNT_GNVS_UPDATE), "b"((uint32_t)gnvs),
-		       "d"(APM_CNT));
-}

src/soc/intel/skylake/acpi.c

@@ -655,7 +655,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/soc/intel/xeon_sp/Kconfig

@@ -38,6 +38,7 @@ config	CPU_SPECIFIC_OPTIONS
 	select POSTCAR_STAGE
 	select IOAPIC
 	select PARALLEL_MP
+	select ACPI_NO_SMI_GNVS
 	select SMP
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/xeon_sp/cpx/acpi.c

@@ -120,7 +120,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* TODO: tell SMI about it, if HAVE_SMI_HANDLER */
-		// smm_setup_structures(gnvs, NULL, NULL);
+		// apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs);

src/soc/intel/xeon_sp/skx/acpi.c

@@ -968,7 +968,7 @@ void southbridge_inject_dsdt(const struct device *device)
 	if (gnvs) {
 		acpi_create_gnvs(gnvs);
 		/* TODO: tell SMI about it, if HAVE_SMI_HANDLER */
-		// smm_setup_structures(gnvs, NULL, NULL);
+		// apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs);

src/southbridge/amd/agesa/hudson/smi.c

@@ -10,11 +10,6 @@
 
 #include "smi.h"
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/southbridge/amd/pi/hudson/smi.c

@@ -10,11 +10,6 @@
 
 #include "smi.h"
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
 /** Set the EOS bit and enable SMI generation from southbridge */
 void global_smi_enable(void)
 {

src/southbridge/intel/bd82x6x/lpc.c

@@ -665,7 +665,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 #endif
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/common/smi.c

@@ -79,25 +79,6 @@ void global_smi_enable(void)
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
 
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((uintptr_t)gnvs),
-		  "d" (APM_CNT)
-	);
-}
-
 void smm_southbridge_clear_state(void)
 {
 	if (smi_enabled())

src/southbridge/intel/i82801gx/lpc.c

@@ -622,7 +622,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 		acpi_create_gnvs(gnvs);
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/i82801ix/lpc.c

@@ -464,7 +464,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 		acpi_create_gnvs(gnvs);
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/i82801jx/lpc.c

@@ -623,7 +623,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 		acpi_create_gnvs(gnvs);
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/ibexpeak/lpc.c

@@ -566,7 +566,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 		gnvs->pcnt = dev_count_cpu();
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to SSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/lynxpoint/lpc.c

@@ -721,7 +721,7 @@ static void southbridge_inject_dsdt(const struct device *dev)
 		gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE);
 
 		/* And tell SMI about it */
-		smm_setup_structures(gnvs, NULL, NULL);
+		apm_control(APM_CNT_GNVS_UPDATE);
 
 		/* Add it to DSDT.  */
 		acpigen_write_scope("\\");

src/southbridge/intel/lynxpoint/smi.c

@@ -57,22 +57,3 @@ void global_smi_enable(void)
 {
 	smm_southbridge_enable(PWRBTN_EN | GBL_EN);
 }
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
-	/*
-	 * Issue SMI to set the gnvs pointer in SMM.
-	 * tcg and smi1 are unused.
-	 *
-	 * EAX = APM_CNT_GNVS_UPDATE
-	 * EBX = gnvs pointer
-	 * EDX = APM_CNT
-	 */
-	asm volatile (
-		"outb %%al, %%dx\n\t"
-		: /* ignore result */
-		: "a" (APM_CNT_GNVS_UPDATE),
-		  "b" ((u32)gnvs),
-		  "d" (APM_CNT)
-	);
-}