mb/system76/*: Enable HECI device
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
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@ -98,7 +98,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -98,7 +98,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -245,7 +245,6 @@ chip soc/intel/tigerlake
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register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
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register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
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end
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end
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device ref heci1 on
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device ref heci1 on
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# TODO Disable ME and HECI
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "1"
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end
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end
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device ref uart2 on
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device ref uart2 on
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@ -256,7 +256,6 @@ chip soc/intel/tigerlake
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register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
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register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
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end
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end
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device ref heci1 on
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device ref heci1 on
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# TODO Disable ME and HECI
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "1"
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end
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end
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device ref uart2 on
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device ref uart2 on
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@ -95,7 +95,7 @@ chip soc/intel/cannonlake
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device pci 15.1 on end # I2C #1
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -226,7 +226,6 @@ chip soc/intel/tigerlake
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register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
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register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
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end
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end
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device ref heci1 on
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device ref heci1 on
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# TODO Disable ME and HECI
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register "HeciEnabled" = "1"
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register "HeciEnabled" = "1"
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end
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end
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device ref uart2 on
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device ref uart2 on
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@ -102,7 +102,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -108,7 +108,7 @@ chip soc/intel/cannonlake
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device pci 15.1 on end # I2C #1
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device pci 15.1 on end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -110,7 +110,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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