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mb/system76/*: Enable HECI device 

The HECI device needs to be enabled to send the commands to have the
CSME change between Soft Temporary Disable mode and Normal mode.

Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
This commit is contained in:
Tim Crawford 2021-10-27 15:14:54 -06:00 committed by Felix Held
parent a6b3af927c
commit c3ced8fa4e
9 changed files with 6 additions and 9 deletions
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2
src/mainboard/system76/addw1/devicetree.cb
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@ -98,7 +98,7 @@ chip soc/intel/cannonlake
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection

2
src/mainboard/system76/cml-u/devicetree.cb
View File

@ -98,7 +98,7 @@ chip soc/intel/cannonlake
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection

1
src/mainboard/system76/darp7/devicetree.cb
View File

@ -245,7 +245,6 @@ chip soc/intel/tigerlake
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
# TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on

1
src/mainboard/system76/galp5/devicetree.cb
View File

@ -256,7 +256,6 @@ chip soc/intel/tigerlake
register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
end
device ref heci1 on
# TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on

2
src/mainboard/system76/gaze15/devicetree.cb
View File

@ -95,7 +95,7 @@ chip soc/intel/cannonlake
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection

1
src/mainboard/system76/lemp10/devicetree.cb
View File

@ -226,7 +226,6 @@ chip soc/intel/tigerlake
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
# TODO Disable ME and HECI
register "HeciEnabled" = "1"
end
device ref uart2 on

2
src/mainboard/system76/lemp9/devicetree.cb
View File

@ -102,7 +102,7 @@ chip soc/intel/cannonlake
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection

2
src/mainboard/system76/oryp5/devicetree.cb
View File

@ -108,7 +108,7 @@ chip soc/intel/cannonlake
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection

2
src/mainboard/system76/oryp6/devicetree.cb
View File

@ -110,7 +110,7 @@ chip soc/intel/cannonlake
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection