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mainboard/google/reef: set SLP_S3_L assertion width to 28ms 

The reef board needs at least ~28ms for its S0 rails to discharge
when S3 is entered. Because of the granularity in the chipset the
effective SLP_S3_L assertion width is 50ms.

BUG=chrome-os-partner:56581

Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16327
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Aaron Durbin 2016-08-25 15:44:39 -05:00
parent 41a3fa66a0
commit c3d74273a7
1 changed files with 3 additions and 0 deletions
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src/mainboard/google/reef/devicetree.cb
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@ -50,6 +50,9 @@ chip soc/intel/apollolake
# Enable I2C2 bus early for TPM access
register "i2c[2].early_init" = "1"
# Minimum SLP S3 assertion width 28ms.
register "slp_s3_assertion_width_usecs" = "28000"
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF