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mb/amd/onyx/devicetree: enable more PCI devices 

Early versions of CB:76519 had more devices enabled in the chipset
devicetree which shouldn't necessarily be enabled in the chipset
devicetree. Enable most of those in the Onyx mainboard's devicetree.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
This commit is contained in:
Felix Held 2023-12-07 23:32:27 +01:00
parent 5aaaee3486
commit c3d909dbb7
1 changed files with 20 additions and 0 deletions
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20
src/mainboard/amd/onyx/devicetree.cb
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@ -54,6 +54,7 @@ chip soc/amd/genoa
device domain 0 on
device ref iommu_0 on end
device ref rcec_0 on end
device ref gpp_bridge_0_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P2
register "start_lane" = "48"
@ -82,10 +83,19 @@ chip soc/amd/genoa
device generic 0 on end
end
end
device ref gpp_bridge_0_a on
device ref xhci_0 on end
device ref mp0_0 on end
end
device ref gpp_bridge_0_b on
device ref sata_0_0 on end
device ref sata_0_1 on end
end
end
device domain 1 on
device ref iommu_1 on end
device ref rcec_1 on end
device ref gpp_bridge_1_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P3
register "start_lane" = "16"
@ -108,6 +118,7 @@ chip soc/amd/genoa
device domain 2 on
device ref iommu_2 on end
device ref rcec_2 on end
device ref gpp_bridge_2_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P1
register "start_lane" = "32"
@ -132,6 +143,7 @@ chip soc/amd/genoa
device domain 3 on
device ref iommu_3 on end
device ref rcec_3 on end
device ref gpp_bridge_3_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P0
register "start_lane" = "0"
@ -178,6 +190,14 @@ chip soc/amd/genoa
device generic 0 on end
end
end
device ref gpp_bridge_3_a on
device ref xhci_3 on end
device ref mp0_3 on end
end
device ref gpp_bridge_3_b on
device ref sata_3_0 on end
device ref sata_3_1 on end
end
end
end