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soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notation 

Prepare for merge with cpx.
Use the C style operators instead of the ACPI1.x polish notation.
This is much easier to read and matches the cpx code.

This generates the same ASL code.
Checked with BUILD_TIMELESS on TiogaPass.

Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marc Jones 2020-09-10 11:12:12 -06:00 committed by Marc Jones
parent b20c1023d6
commit c3d92f0c73
1 changed files with 2 additions and 4 deletions
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6
src/soc/intel/xeon_sp/skx/acpi/pci_irq.asl
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@ -8,10 +8,8 @@
* PIRQ routing control is in PCR ITSS region.
*/
OperationRegion (ITSS, SystemMemory,
Add (PCR_ITSS_PIRQA_ROUT,
Add (CONFIG_PCR_BASE_ADDRESS,
ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)
OperationRegion (ITSS, SystemMemory, PCR_ITSS_PIRQA_ROUT +
CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), 8)
Field (ITSS, ByteAcc, NoLock, Preserve)
{
PIRA, 8, /* PIRQA Routing Control */