mb/google/kahlee: Init APU_BIOS_FLASH_WP_L GPIO to reset stage
GPIO APU_BIOS_FLASH_WP_L is first read in ROM stage to determine the state of the BIOS FLASH Write Protect signal at boot. The result of this read accumulated in the vboot state that's passed on to the upper layers of the stack. Therefore this GPIO must be configured as a "reset stage" GPIO, not a "RAM" stage GPIO. BUG=b:79866233 TEST=firmware_WriteProtect Change-Id: I1d96ab4bbfeaf9db9f74cf0c58cbab2104079bf7 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26498 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
2df1c124c4
commit
c3e7416b1b
|
@ -58,6 +58,9 @@ static const struct soc_amd_gpio gpio_set_stage_reset_old[] = {
|
|||
/* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */
|
||||
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
|
||||
|
||||
/* GPIO_122 - APU_BIOS_FLASH_WP_L */
|
||||
PAD_GPI(GPIO_122, PULL_NONE),
|
||||
|
||||
/* GPIO_131 - CONFIG_STRAP3 */
|
||||
PAD_GPI(GPIO_131, PULL_NONE),
|
||||
|
||||
|
@ -111,6 +114,9 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
|
|||
/* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */
|
||||
PAD_NF(GPIO_92, CLK_REQ0_L, PULL_UP),
|
||||
|
||||
/* GPIO_122 - APU_BIOS_FLASH_WP_L */
|
||||
PAD_GPI(GPIO_122, PULL_NONE),
|
||||
|
||||
/* GPIO_131 - CONFIG_STRAP3 */
|
||||
PAD_GPI(GPIO_131, PULL_NONE),
|
||||
|
||||
|
@ -251,9 +257,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram_old[] = {
|
|||
/* GPIO_119 - SPK_PA_EN */
|
||||
PAD_GPO(GPIO_119, HIGH),
|
||||
|
||||
/* GPIO_122 - APU_BIOS_FLASH_WP_L */
|
||||
PAD_GPI(GPIO_122, PULL_NONE),
|
||||
|
||||
/* GPIO_126 - DMIC_CLK2_EN */
|
||||
PAD_GPO(GPIO_126, HIGH),
|
||||
|
||||
|
@ -415,9 +418,6 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
|
|||
/* GPIO_119 - SPK_PA_EN */
|
||||
PAD_GPO(GPIO_119, HIGH),
|
||||
|
||||
/* GPIO_122 - APU_BIOS_FLASH_WP_L */
|
||||
PAD_GPI(GPIO_122, PULL_NONE),
|
||||
|
||||
/* GPIO_126 - DMIC_CLK2_EN */
|
||||
PAD_GPO(GPIO_126, HIGH),
|
||||
|
||||
|
|
Loading…
Reference in New Issue