From c3e75b42a471cc64fec37a464eef7088492ec04e Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 15 Jan 2019 17:37:50 -0800 Subject: [PATCH] soc/intel/cannonlake: Fix afterg3 programming According to EDS #565870 chapter 5.3.1, AG3E bit in PMC located in PMC memory mapped register but not pci config spaces. Change the programming to affect that difference. BUG=b:122425492 TEST=Change System Power State after failure to "s5 off", and boot up onto sarien platform, check the register with iotools mmio_read32 0xfe001020 and bit 0 is set. Signed-off-by: Lijian Zhao Change-Id: I0934894558fd9cbc056dea8e7ac30426c2529e4e Reviewed-on: https://review.coreboot.org/c/30945 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/pmc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index aebcfc9482..4dabb2ecef 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,8 +33,9 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) { uint8_t reg8; + uint8_t *pmcbase = pmc_mmio_regs(); - reg8 = pci_read_config8(dev, GEN_PMCON_B); + reg8 = read8(pmcbase + GEN_PMCON_A); switch (s5pwr) { case MAINBOARD_POWER_STATE_OFF: @@ -48,7 +49,7 @@ static void pmc_set_afterg3(struct device *dev, int s5pwr) break; } - pci_write_config8(dev, GEN_PMCON_B, reg8); + write8(pmcbase + GEN_PMCON_A, reg8); } /*