nb/intel/gm45: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Tested on Lenovo thinkpad X200: on cold boot the external stage cache gets created and the cached ramstage gets successfully used on the S3 resume path. Change-Id: I642f7d6ae5523a35904c8e1f029027565a364d26 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/25604 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -30,6 +30,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
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select POSTCAR_CONSOLE
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select SMM_TSEG
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select PARALLEL_MP
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
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config CBFS_SIZE
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hex
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@ -47,4 +48,8 @@ config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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endif
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@ -38,4 +38,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
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postcar-y += ram_calc.c
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romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
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endif
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@ -0,0 +1,32 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <cbmem.h>
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#include <device/pci.h>
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#include <stage_cache.h>
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#include <cpu/intel/smm/gen1/smi.h>
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#include "gm45.h"
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void stage_cache_external_region(void **base, size_t *size)
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{
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/*
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* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
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* The top of RAM is defined to be the TSEG base address.
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*/
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*size = CONFIG_SMM_RESERVED_SIZE;
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*base = (void *)(northbridge_get_tseg_base()
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+ CONFIG_SMM_RESERVED_SIZE);
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}
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