diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 127173827e..6ff9d02b34 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -53,6 +53,7 @@
 #define	AMD_GT_F0	(AMD_NPT_ALL AND NOT AMD_NPT_F0)
 #define	AMD_DR_Ax	(AMD_DR_A0A + AMD_DR_A1B + AMD_DR_A2)
 #define	AMD_DR_Bx	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_B3 | AMD_DR_BA)
+#define	AMD_DR_LT_B2	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_BA)
 #define	AMD_DR_LT_B3	(AMD_DR_B0 | AMD_DR_B1 | AMD_DR_B2 | AMD_DR_BA)
 #define	AMD_DR_GT_B0	(AMD_DR_ALL & ~(AMD_DR_B0))
 #define	AMD_DR_ALL	(AMD_DR_Bx)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index f29953a5c6..693500e40c 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -2401,30 +2401,34 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
 	mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat);
 	// FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
 
-	/* Disable auto refresh before Dram init when in ganged mode */
-	if (pDCTstat->GangedMode) {
-		val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-		val |= 1 << DisAutoRefresh;
-		Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+	/* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
+	if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+		if (pDCTstat->GangedMode) {
+			val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+			val |= 1 << DisAutoRefresh;
+			Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+		}
 	}
 
 	mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct);
 
 	/* Re-enable auto refresh after Dram init when in ganged mode
-	 * to ensure both DCTs are in sync
+	 * to ensure both DCTs are in sync (Erratum 278)
 	 */
 
-	if (pDCTstat->GangedMode) {
-		do {
-			val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
-		} while (!(val & (1 << InitDram)));
+	if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+		if (pDCTstat->GangedMode) {
+			do {
+				val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
+			} while (!(val & (1 << InitDram)));
 
-		WaitRoutine_D(50);
+			WaitRoutine_D(50);
 
-		val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-		val &= ~(1 << DisAutoRefresh);
-		val |= 1 << DisAutoRefresh;
-		val &= ~(1 << DisAutoRefresh);
+			val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+			val &= ~(1 << DisAutoRefresh);
+			val |= 1 << DisAutoRefresh;
+			val &= ~(1 << DisAutoRefresh);
+		}
 	}
 }
 
@@ -3792,7 +3796,10 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 	u8 wrap32dis = 0;
 	u8 valid = 0;
 
-	/* FIXME: Skip reset DLL for B3 */
+	/* Skip reset DLL for B3 */
+	if (pDCTstat->LogicalCPUID & AMD_DR_B3) {
+		return;
+	}
 
 	addr = HWCR;
 	_RDMSR(addr, &lo, &hi);
@@ -3885,8 +3892,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
 	u32 reg_off = 0x100 * dct;
 	u32 dev = pDCTstat->dev_dct;
 
-	/* FIXME: Add B3 */
-	if (pDCTstat->LogicalCPUID & AMD_DR_B2) {
+	if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
 		mct_Wait(10000);	/* Wait 50 us*/
 		val = Get_NB32(dev, 0x110);
 		if ( val & (1 << DramEnabled)) {