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mainboard/google/kahlee: Set EMMC reset pin to output low 

While the pin was set to a pull-down, with the external pull-up, this
wasn't enough to keep the pin low.  Set to output low to drive to 0V.

TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V.
BUG=b:115661061

Change-Id: Ife014b8a879274df5d892c1de386976808de1df0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Martin Roth 2018-09-17 09:16:31 -06:00
parent 6b3038efc0
commit c3f5293da7
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/kahlee/variants/baseboard/gpio.c
View File

@ -54,7 +54,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* GPIO_40 - EMMC_BRIDGE_RST */ /* GPIO_40 - EMMC_BRIDGE_RST */
PAD_GPI(GPIO_40, PULL_DOWN), PAD_GPO(GPIO_40, LOW),
/* GPIO_70 - WLAN_PE_RST_L */ /* GPIO_70 - WLAN_PE_RST_L */
PAD_GPO(GPIO_70, HIGH), PAD_GPO(GPIO_70, HIGH),