southbridge/amd/sr5650: Fix boot failure on ASUS KGPE-D16
Change-Id: Ia13ba58118a826e830a4dc6e2378b76110fcabad Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11939 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
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@ -0,0 +1,388 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2009 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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Scope(\) {
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Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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/* PIC IRQ mapping registers, C00h-C01h */
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OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
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Field(PRQM, ByteAcc, NoLock, Preserve) {
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PRQI, 0x00000008,
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PRQD, 0x00000008, /* Offset: 1h */
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}
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IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PINA, 0x00000008, /* Index 0 */
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PINB, 0x00000008, /* Index 1 */
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PINC, 0x00000008, /* Index 2 */
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PIND, 0x00000008, /* Index 3 */
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AINT, 0x00000008, /* Index 4 */
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SINT, 0x00000008, /* Index 5 */
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, 0x00000008, /* Index 6 */
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AAUD, 0x00000008, /* Index 7 */
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AMOD, 0x00000008, /* Index 8 */
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PINE, 0x00000008, /* Index 9 */
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PINF, 0x00000008, /* Index A */
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PING, 0x00000008, /* Index B */
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PINH, 0x00000008, /* Index C */
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}
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/* PCI Error control register */
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OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
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Field(PERC, ByteAcc, NoLock, Preserve) {
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SENS, 0x00000001,
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PENS, 0x00000001,
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SENE, 0x00000001,
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PENE, 0x00000001,
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}
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Scope(\_SB) {
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/* PCIe Configuration Space for 16 busses */
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OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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*/
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Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
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STB5, 32,
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Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
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PT0D, 1,
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PT1D, 1,
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PT2D, 1,
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PT3D, 1,
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PT4D, 1,
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PT5D, 1,
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PT6D, 1,
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PT7D, 1,
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PT8D, 1,
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PT9D, 1,
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Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
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SBIE, 1,
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SBME, 1,
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Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
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SBRI, 8,
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Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
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SBB1, 32,
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Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
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,14,
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P92E, 1, /* Port92 decode enable */
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}
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OperationRegion(SB5, SystemMemory, STB5, 0x1000)
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Field(SB5, AnyAcc, NoLock, Preserve){
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/* Port 0 */
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Offset(0x120), /* Port 0 Task file status */
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P0ER, 1,
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, 2,
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P0DQ, 1,
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, 3,
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P0BY, 1,
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Offset(0x128), /* Port 0 Serial ATA status */
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P0DD, 4,
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, 4,
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P0IS, 4,
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Offset(0x12C), /* Port 0 Serial ATA control */
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P0DI, 4,
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Offset(0x130), /* Port 0 Serial ATA error */
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, 16,
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P0PR, 1,
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/* Port 1 */
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offset(0x1A0), /* Port 1 Task file status */
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P1ER, 1,
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, 2,
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P1DQ, 1,
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, 3,
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P1BY, 1,
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Offset(0x1A8), /* Port 1 Serial ATA status */
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P1DD, 4,
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, 4,
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P1IS, 4,
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Offset(0x1AC), /* Port 1 Serial ATA control */
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P1DI, 4,
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Offset(0x1B0), /* Port 1 Serial ATA error */
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, 16,
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P1PR, 1,
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/* Port 2 */
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Offset(0x220), /* Port 2 Task file status */
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P2ER, 1,
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, 2,
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P2DQ, 1,
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, 3,
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P2BY, 1,
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Offset(0x228), /* Port 2 Serial ATA status */
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P2DD, 4,
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, 4,
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P2IS, 4,
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Offset(0x22C), /* Port 2 Serial ATA control */
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P2DI, 4,
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Offset(0x230), /* Port 2 Serial ATA error */
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, 16,
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P2PR, 1,
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/* Port 3 */
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Offset(0x2A0), /* Port 3 Task file status */
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P3ER, 1,
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, 2,
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P3DQ, 1,
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, 3,
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P3BY, 1,
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Offset(0x2A8), /* Port 3 Serial ATA status */
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P3DD, 4,
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, 4,
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P3IS, 4,
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Offset(0x2AC), /* Port 3 Serial ATA control */
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P3DI, 4,
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Offset(0x2B0), /* Port 3 Serial ATA error */
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, 16,
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P3PR, 1,
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}
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Method(CIRQ, 0x00, NotSerialized){
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Store(0, PINA)
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Store(0, PINB)
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Store(0, PINC)
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Store(0, PIND)
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Store(0, PINE)
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Store(0, PINF)
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Store(0, PING)
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Store(0, PINH)
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}
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/* set "A", 8259 interrupts */
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Name (PRSA, ResourceTemplate () {
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IRQ(Level, ActiveLow, Exclusive) {4, 7, 10, 11, 12, 14, 15}
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})
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Method (CRSA, 1, Serialized) {
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Name (LRTL, ResourceTemplate() {
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IRQ(Level, ActiveLow, Shared) {15}
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})
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CreateWordField(LRTL, 1, LIRQ)
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ShiftLeft(1, Arg0, LIRQ)
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Return (LRTL)
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}
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Method (SRSA, 1, Serialized) {
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CreateWordField(Arg0, 1, LIRQ)
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FindSetRightBit(LIRQ, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Return (Local0)
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}
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Device(LNKA) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 1)
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Method(_STA, 0) {
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if (PINA) {
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Return(0x0B) /* LNKA is invisible */
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} else {
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Return(0x09) /* LNKA is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINA)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINA))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINA)
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}
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}
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Device(LNKB) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 2)
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Method(_STA, 0) {
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if (PINB) {
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Return(0x0B) /* LNKB is invisible */
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} else {
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Return(0x09) /* LNKB is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINB)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINB))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINB)
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}
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}
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Device(LNKC) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 3)
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Method(_STA, 0) {
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if (PINC) {
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Return(0x0B) /* LNKC is invisible */
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} else {
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Return(0x09) /* LNKC is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINC)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINC))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINC)
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}
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}
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Device(LNKD) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 4)
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Method(_STA, 0) {
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if (PIND) {
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Return(0x0B) /* LNKD is invisible */
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} else {
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Return(0x09) /* LNKD is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PIND)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PIND))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PIND)
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}
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}
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Device(LNKE) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 5)
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Method(_STA, 0) {
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if (PINE) {
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Return(0x0B) /* LNKE is invisible */
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} else {
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Return(0x09) /* LNKE is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINE)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINE))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINE)
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}
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}
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Device(LNKF) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 6)
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Method(_STA, 0) {
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if (PINF) {
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Return(0x0B) /* LNKF is invisible */
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} else {
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Return(0x09) /* LNKF is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINF)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINF))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINF)
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}
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}
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Device(LNKG) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 7)
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Method(_STA, 0) {
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if (PING) {
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Return(0x0B) /* LNKG is invisible */
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} else {
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Return(0x09) /* LNKG is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PING)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PING))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PING)
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}
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}
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Device(LNKH) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 8)
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Method(_STA, 0) {
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if (PINH) {
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Return(0x0B) /* LNKH is invisible */
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} else {
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Return(0x09) /* LNKH is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINH)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINH))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINH)
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}
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}
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} /* End Scope(_SB) */
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} /* End Scope(/) */
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -504,7 +505,8 @@ void sr5650_early_setup(void)
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/*ATINB_PrepareInit */
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get_cpu_rev();
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switch (get_nb_rev(nb_dev)) { /* PCIEMiscInit */
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uint8_t revno = get_nb_rev(nb_dev);
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switch (revno) { /* PCIEMiscInit */
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case REV_SR5650_A11:
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printk(BIOS_INFO, "NB Revision is A11.\n");
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break;
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@ -514,6 +516,9 @@ void sr5650_early_setup(void)
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case REV_SR5650_A21:
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printk(BIOS_INFO, "NB Revision is A21.\n");
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break;
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default:
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printk(BIOS_INFO, "NB Revision is %02x (Unrecognized).\n", revno);
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break;
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}
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fam10_optimization();
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|
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
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*
|
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
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|
@ -55,7 +56,7 @@ static const apic_device_info default_apic_device_info_t [] = {
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[13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */
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};
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/* Their name are quite regular. So I undefine them. */
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/* These define names are common, so undefine them to avoid potential issues in other code */
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#undef ABCD
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#undef BCDA
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#undef CDAB
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|
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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||||
*
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||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -61,8 +62,10 @@ static void ValidatePortEn(device_t nb_dev)
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*****************************************************************/
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static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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{
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printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port);
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u32 reg;
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u16 state_save;
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uint8_t i;
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struct southbridge_amd_sr5650_config *cfg =
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(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
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u16 state = cfg->port_enable;
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|
@ -72,6 +75,28 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
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state = ~state;
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state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
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state_save = state << 17;
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/* Disable ports any that failed training */
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for (i = 9; i <= 13; i++) {
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if (!(AtiPcieCfg.PortDetect & 1 << i)) {
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if ((port >= 9) && (port <= 13)) {
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state |= (1 << (port + 7));
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}
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if (port == 9)
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state_save |= 1 << 25;
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if (port == 10)
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state_save |= 1 << 26;
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if (port == 11)
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state_save |= 1 << 6;
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if (port == 12)
|
||||
state_save |= 1 << 7;
|
||||
|
||||
if (port == 13) {
|
||||
reg = nbmisc_read_index(nb_dev, 0x2a);
|
||||
reg |= 1 << 4;
|
||||
nbmisc_write_index(nb_dev, 0x2a, reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
state &= !(AtiPcieCfg.PortHp);
|
||||
reg = nbmisc_read_index(nb_dev, 0x0c);
|
||||
reg |= state;
|
||||
|
@ -483,6 +508,8 @@ static void EnableLclkGating(device_t dev)
|
|||
*****************************************/
|
||||
void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
||||
{
|
||||
uint8_t training_ok = 1;
|
||||
|
||||
u32 gpp_sb_sel = 0;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
@ -744,6 +771,12 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
|||
port, hw_port, res);
|
||||
if (res) {
|
||||
AtiPcieCfg.PortDetect |= 1 << port;
|
||||
} else {
|
||||
/* If the training failed the disable the bridge to prevent subsequent
|
||||
* lockup on bridge configuration register read during the PCI bus scan
|
||||
*/
|
||||
training_ok = 0;
|
||||
dev->enabled = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -790,8 +823,8 @@ void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
|
|||
* wait dev 0x6B bit3 clear
|
||||
*/
|
||||
|
||||
if (port == 8){
|
||||
PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */
|
||||
if ((port == 8) || (!training_ok)) {
|
||||
PciePowerOffGppPorts(nb_dev, dev, port); /* This is run for all ports that are not hotplug and don't detect devices */
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
@ -95,25 +96,24 @@ void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data)
|
|||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
|
||||
{
|
||||
/* K8 Function1 is address map */
|
||||
device_t k8_f1;
|
||||
device_t np = dev_find_slot(0, PCI_DEVFN(0x19, 1));
|
||||
u16 node;
|
||||
|
||||
for (node = 0; node < CONFIG_MAX_PHYSICAL_CPUS; node++) {
|
||||
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1));
|
||||
if (!k8_f1) {
|
||||
break;
|
||||
}
|
||||
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
|
||||
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
|
||||
|
||||
if (in_out) {
|
||||
u32 dword, sblk;
|
||||
|
||||
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
|
||||
dword = pci_read_config32(k8_f0, 0x64);
|
||||
sblk = (dword >> 8) & 0x3;
|
||||
|
||||
/* Fill MMIO limit/base pair. */
|
||||
pci_write_config32(k8_f1, 0xbc,
|
||||
(((pcie_base_add + 0x10000000 -
|
||||
1) >> 8) & 0xffffff00) | 0x8 | (np ? 2 << 4 : 0 << 4));
|
||||
1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
|
||||
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
|
||||
pci_write_config32(k8_f1, 0xb4,
|
||||
((mmio_base_add + 0x10000000 -
|
||||
1) >> 8) | (np ? 2 << 4 : 0 << 4));
|
||||
(((mmio_base_add + 0x10000000 -
|
||||
1) >> 8) & 0xffffff00) | (sblk << 4));
|
||||
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
|
||||
} else {
|
||||
pci_write_config32(k8_f1, 0xb8, 0);
|
||||
|
@ -121,7 +121,6 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
|
|||
pci_write_config32(k8_f1, 0xb0, 0);
|
||||
pci_write_config32(k8_f1, 0xb4, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port)
|
||||
|
|
Loading…
Reference in New Issue