Whitespace and style cleanup. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Jones
parent
8d183c5846
commit
c4128cfbec
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@ -68,7 +68,8 @@ static inline void print_t(const char *strval)
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#include "amdk8_f_pci.c"
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// for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data
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/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
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and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
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/*
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index:
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[29: 0] DctOffset (Dram Controller Offset)
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@ -83,14 +84,14 @@ static inline void print_t(const char *strval)
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[31: 0] DctOffsetData (Dram Controller Offset Data)
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Read:
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- Write the register num to DctOffset with DctAccessWrite = 0
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- Write the register num to DctOffset with
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DctAccessWrite = 0
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- poll the DctAccessDone until it = 1
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- Read the data from DctOffsetData
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Write:
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- Write the data to DctOffsetData
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- Write register num to DctOffset with DctAccessWrite = 1
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- poll the DctAccessDone untio it = 1
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*/
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@ -119,7 +120,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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{
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static const unsigned int register_values[] = {
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/* Careful set limit registers before base registers which contain the enables */
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/* Careful set limit registers before base registers which
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contain the enables */
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/* DRAM Limit i Registers
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* F1:0x44 i = 0
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* F1:0x4C i = 1
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@ -260,7 +262,9 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 111 = Reseved
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* [15: 7] Reserved
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* [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable)
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* Enables the DDR memory clocks to be tristated when alternate VID mode is enabled. This bit has no effect if the DisNbClkRamp bit (F3, 0x88) is set
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* Enables the DDR memory clocks to be tristated when alternate VID
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* mode is enabled. This bit has no effect if the DisNbClkRamp bit
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* (F3, 0x88) is set
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* [17:17] DllTempAdjTime (DLL Temperature Adjust Cycle Time)
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* 0 = 5 ms
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* 1 = 1 ms
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@ -274,23 +278,36 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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/* DRAM Initialization Register
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* F2:0x7C
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* [15: 0] MrsAddress (Address for MRS/EMRS Commands)
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* this field specifies the dsata driven on the DRAM address pins 15-0 for MRS and EMRS commands
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* this field specifies the dsata driven on the DRAM address pins
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* 15-0 for MRS and EMRS commands
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* [18:16] MrsBank (Bank Address for MRS/EMRS Commands)
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* this files specifies the data driven on the DRAM bank pins for the MRS and EMRS commands
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* this files specifies the data driven on the DRAM bank pins for
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* the MRS and EMRS commands
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* [23:19] reverved
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* [24:24] SendPchgAll (Send Precharge All Command)
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* Setting this bit causes the DRAM controller to send a precharge all command. This bit is cleared by the hardware after the command completes
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* Setting this bit causes the DRAM controller to send a precharge
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* all command. This bit is cleared by the hardware after the
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* command completes
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* [25:25] SendAutoRefresh (Send Auto Refresh Command)
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* Setting this bit causes the DRAM controller to send an auto refresh command. This bit is cleared by the hardware after the command completes
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* Setting this bit causes the DRAM controller to send an auto
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* refresh command. This bit is cleared by the hardware after the
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* command completes
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* [26:26] SendMrsCmd (Send MRS/EMRS Command)
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* Setting this bit causes the DRAM controller to send the MRS or EMRS command defined by the MrsAddress and MrsBank fields. This bit is cleared by the hardware adter the commmand completes
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* Setting this bit causes the DRAM controller to send the MRS or
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* EMRS command defined by the MrsAddress and MrsBank fields. This
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* bit is cleared by the hardware adter the commmand completes
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* [27:27] DeassertMemRstX (De-assert Memory Reset)
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* Setting this bit causes the DRAM controller to de-assert the memory reset pin. This bit cannot be used to assert the memory reset pin
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* Setting this bit causes the DRAM controller to de-assert the
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* memory reset pin. This bit cannot be used to assert the memory
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* reset pin
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* [28:28] AssertCke (Assert CKE)
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* setting this bit causes the DRAM controller to assert the CKE pins. This bit cannot be used to de-assert the CKE pins
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* setting this bit causes the DRAM controller to assert the CKE
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* pins. This bit cannot be used to de-assert the CKE pins
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* [30:29] reverved
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* [31:31] EnDramInit (Enable DRAM Initialization)
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* Setting this bit puts the DRAM controller in a BIOS controlled DRAM initialization mode. BIOS must clear this bit aster DRAM initialization is complete.
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* Setting this bit puts the DRAM controller in a BIOS controlled
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* DRAM initialization mode. BIOS must clear this bit aster DRAM
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* initialization is complete.
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*/
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// PCI_ADDR(0, 0x18, 2, 0x7C), 0x60f80000, 0,
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@ -353,13 +370,15 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 0010 = 5 bus clocks
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* ...
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* 1111 = 18 bus clocks
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* [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto refresh of the same bank)
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* [19:16] Trc (Row Cycle Time, Ras#-active to Ras#-active or auto
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* refresh of the same bank)
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* 0000 = 11 bus clocks
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* 0010 = 12 bus clocks
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* ...
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* 1110 = 25 bus clocks
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* 1111 = 26 bus clocks
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* [21:20] Twr (Write Recovery Time, From the last data to precharge, writes can go back-to-back)
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* [21:20] Twr (Write Recovery Time, From the last data to precharge,
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* writes can go back-to-back)
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* 00 = 3 bus clocks
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* 01 = 4 bus clocks
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* 10 = 5 bus clocks
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@ -369,7 +388,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 01 = 3 bus clocks
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* 10 = 4 bus clocks
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* 11 = 5 bus clocks
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* [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A, BIOS should set it to reduce the power consumption)
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* [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
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* BIOS should set it to reduce the power consumption)
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* Bit F(1207) M2 Package S1g1 Package
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* 0 N/A MA1_CLK1 N/A
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* 1 N/A MA0_CLK1 MA0_CLK1
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@ -394,12 +414,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 110 = 8 bus clocks
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* 111 = 9 bus clocks
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* [ 7: 7] Reserved
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* [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, minium write-to-read delay when both access the same chip select)
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* [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay,
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* minium write-to-read delay when both access the same chip select)
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* 00 = Reserved
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* 01 = 1 bus clocks
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* 10 = 2 bus clocks
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* 11 = 3 bus clocks
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* [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum write-to-read delay when accessing two different DIMMs)
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* [11:10] Twrrd (Write to Read DIMM Termination Turnaround, minimum
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* write-to-read delay when accessing two different DIMMs)
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* 00 = 0 bus clocks
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* 01 = 1 bus clocks
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* 10 = 2 bus clocks
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@ -420,7 +442,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 10 = Refresh interval of 7.8 microseconds
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* 11 = Refresh interval of 3.9 microseconds
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* [19:18] Reserved
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* [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0, based on DRAM density and speed)
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* [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
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* based on DRAM density and speed)
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* 000 = 75 ns (all speeds, 256Mbit)
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* 001 = 105 ns (all speeds, 512Mbit)
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* 010 = 127.5 ns (all speeds, 1Gbit)
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@ -429,17 +452,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 101 = reserved
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* 110 = reserved
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* 111 = reserved
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* [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1, based on DRAM density and speed)
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* [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2, based on DRAM density and speed)
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* [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3, based on DRAM density and speed)
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* [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
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* based on DRAM density and speed)
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* [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
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* based on DRAM density and speed)
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* [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
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* based on DRAM density and speed)
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*/
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PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
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/* DRAM Config Low Register
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* F2:0x90
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* [ 0: 0] InitDram (Initialize DRAM)
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* 1 = write 1 cause DRAM controller to execute the DRAM initialization, when done it read to 0
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* 1 = write 1 cause DRAM controller to execute the DRAM
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* initialization, when done it read to 0
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* [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
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* 1 = write 1 causes the DRAM controller to bring the DRAMs out fo self refresh mode
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* 1 = write 1 causes the DRAM controller to bring the DRAMs out
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* for self refresh mode
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* [ 3: 2] Reserved
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* [ 5: 4] DramTerm (DRAM Termination)
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* 00 = On die termination disabled
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@ -451,9 +479,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 0 = Normal drive strength mode.
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* 1 = Weak drive strength mode
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* [ 8: 8] ParEn (Parity Enable)
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* 1 = Enable address parity computation output, PAR, and enables the parity error input, ERR
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* 1 = Enable address parity computation output, PAR,
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* and enables the parity error input, ERR
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* [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
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* 1 = Enable high temperature ( two times normal ) self refresh rate
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* 1 = Enable high temperature ( two times normal )
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* self refresh rate
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* [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
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* 0 = 64-byte mode
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* 1 = 32-byte mode
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@ -471,7 +501,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 1 = Unbuffered DIMMs
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* [18:17] Reserved
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* [19:19] DimmEccEn ( DIMM ECC Enable )
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1 = ECC checking is being enabled for all DIMMs on the DRAM controller ( Through F3 0x44[EccEn])
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* 1 = ECC checking is being enabled for all DIMMs on the DRAM
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* controller ( Through F3 0x44[EccEn])
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* [31:20] Reserved
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*/
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PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
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@ -484,17 +515,21 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 011 = reserved
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* 1xx = reserved
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* [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid)
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* 1 = BIOS need to set the bit when setting up MemClkFreq to the proper value
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* 1 = BIOS need to set the bit when setting up MemClkFreq to
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* the proper value
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* [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
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* 0000 = 0 ns
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* ...
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* 1111 = 15 ns
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* [11: 8] Reserved
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* [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8 registered DIMMs are present in the system
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* [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
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* registered DIMMs are present in the system
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* 0 = DM pins function as data mask pins
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* 1 = DM pins function as read DQS pins
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* [13:13] Reserved
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* [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit is set, the DRAM controller is disabled, and interface in low power state
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* [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
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* is set, the DRAM controller is disabled, and interface in low power
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* state
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* 0 = Enabled (default)
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* 1 = Disabled
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* [15:15] PowerDownEn ( Power Down Mode Enable )
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@ -504,13 +539,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 0 = Channel CKE Control
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* 1 = Chip Select CKE Control
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* [17:17] FourRankSODimm (Four Rank SO-DIMM)
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* 1 = this bit is set by BIOS to indicate that a four rank SO-DIMM is present
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* 1 = this bit is set by BIOS to indicate that a four rank
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* SO-DIMM is present
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* [18:18] FourRankRDimm (Four Rank Registered DIMM)
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* 1 = this bit is set by BIOS to indicate that a four rank registered DIMM is present
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* 1 = this bit is set by BIOS to indicate that a four rank
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* registered DIMM is present
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* [19:19] Reserved
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* [20:20] SlowAccessMode (Slow Access Mode (2T Mode))
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* 0 = DRAM address and control signals are driven for one MEMCLK cycle
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* 1 = One additional MEMCLK of setup time is provided on all DRAM address and control signals except CS, CKE, and ODT; i.e., these signals are drivern for two MEMCLK cycles rather than one
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* 0 = DRAM address and control signals are driven for one
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* MEMCLK cycle
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* 1 = One additional MEMCLK of setup time is provided on all
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* DRAM address and control signals except CS, CKE, and ODT;
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* i.e., these signals are drivern for two MEMCLK cycles
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* rather than one
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* [21:21] Reserved
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* [22:22] BankSwizzleMode ( Bank Swizzle Mode),
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* 0 = Disabled (default)
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@ -520,8 +561,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 0000 = No bypass; the oldest request is never bypassed
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* 0001 = The oldest request may be bypassed no more than 1 time
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* ...
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* 1111 = The oldest request may be bypassed no more than 15 times
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* [31:28] FourActWindow ( Four Bank Activate Window) , not more than 4 banks in a 8 bank device are activated
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* 1111 = The oldest request may be bypassed no more than 15\
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* times
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* [31:28] FourActWindow ( Four Bank Activate Window) , not more than
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* 4 banks in a 8 bank device are activated
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* 0000 = No tFAW window restriction
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* 0001 = 8 MEMCLK cycles
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* 0010 = 9 MEMCLK cycles
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@ -532,19 +575,27 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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PCI_ADDR(0, 0x18, 2, 0x94), 0x00a82f00,0x00008000,
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/* DRAM Delay Line Register
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* F2:0xa0
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* [ 0: 0] MemClrStatus (Memory Clear Status) : ---------Readonly
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* when set, this bit indicates that the memory clear function is complete. Only clear by reset. BIOS should not write or read the DRAM until this bit is set by hardware
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* [ 0: 0] MemClrStatus (Memory Clear Status) : Readonly
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* when set, this bit indicates that the memory clear function
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* is complete. Only clear by reset. BIOS should not write or
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* read the DRAM until this bit is set by hardware
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* [ 1: 1] DisableJitter ( Disable Jitter)
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* When set the DDR compensation circuit will not change the values unless the change is more than one step from the current value
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* When set the DDR compensation circuit will not change the
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* values unless the change is more than one step from the
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* current value
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* [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
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* 00 = 2
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* 01 = 4
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* 10 = 8
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* 11 = 16
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* [ 4: 4] Mode64BitMux (Mismatched DIMM Support Enable)
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* 1 When bit enables support for mismatched DIMMs when using 128-bit DRAM interface, the Width128 no effect, only for M2 and s1g1
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* 1 When bit enables support for mismatched DIMMs when using
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* 128-bit DRAM interface, the Width128 no effect, only for
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* AM2 and s1g1
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* [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable)
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* When set to 1, indicates that each entry in the page tables dynamically adjusts the idle cycle limit based on page Conflict/Page Miss (PC/PM) traffic
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* When set to 1, indicates that each entry in the page tables
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* dynamically adjusts the idle cycle limit based on page
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* Conflict/Page Miss (PC/PM) traffic
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* [ 8: 6] ILD_lmt ( Idle Cycle Limit)
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* 000 = 0 cycles
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* 001 = 4 cycles
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@ -555,11 +606,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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* 110 = 128 cycles
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* 111 = 256 cycles
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* [ 9: 9] DramEnabled ( DRAM Enabled)
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* When Set, this bit indicates that the DRAM is enabled, this bit is set by hardware after DRAM initialization or on an exit from self refresh. The DRAM controller is intialized after the
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* hardware-controlled initialization process ( initiated by the F2 0x90[DramInit]) completes or when the BIOS-controlled initialization process completes (F2 0x7c(EnDramInit] is
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* When Set, this bit indicates that the DRAM is enabled, this
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* bit is set by hardware after DRAM initialization or on an exit
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* from self refresh. The DRAM controller is intialized after the
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* hardware-controlled initialization process ( initiated by the
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* F2 0x90[DramInit]) completes or when the BIOS-controlled
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* initialization process completes (F2 0x7c(EnDramInit] is
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* written from 1 to 0)
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* [23:10] Reserved
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* [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B, BIOS should set it to reduce the power consumption)
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* [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
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* BIOS should set it to reduce the power consumption)
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* Bit F(1207) M2 Package S1g1 Package
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* 0 N/A MA1_CLK1 N/A
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* 1 N/A MA0_CLK1 MA0_CLK1
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@ -622,7 +678,8 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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*/
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PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000,
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};
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// for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data
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/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
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and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
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/*
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index:
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[29: 0] DctOffset (Dram Controller Offset)
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@ -674,6 +731,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
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print_spew("done.\r\n");
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}
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static int is_dual_channel(const struct mem_controller *ctrl)
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{
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uint32_t dcl;
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@ -681,6 +739,7 @@ static int is_dual_channel(const struct mem_controller *ctrl)
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return dcl & DCL_Width128;
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}
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static int is_opteron(const struct mem_controller *ctrl)
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{
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/* Test to see if I am an Opteron.
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@ -694,6 +753,7 @@ static int is_opteron(const struct mem_controller *ctrl)
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return !!(nbcap & NBCAP_128Bit);
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||||
}
|
||||
|
||||
|
||||
static int is_registered(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* Test to see if we are dealing with registered SDRAM.
|
||||
|
|
@ -705,6 +765,7 @@ static int is_registered(const struct mem_controller *ctrl)
|
|||
return !(dcl & DCL_UnBuffDimm);
|
||||
}
|
||||
|
||||
|
||||
static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
|
||||
{
|
||||
/* Calculate the log base 2 size of a DIMM in bits */
|
||||
|
|
@ -716,13 +777,13 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
|
|||
|
||||
value = spd_read_byte(device, SPD_ROW_NUM); /* rows */
|
||||
if (value < 0) goto hw_err;
|
||||
if ((value & 0xff) == 0) goto val_err; // max is 16 ?
|
||||
if ((value & 0xff) == 0) goto val_err; /* max is 16 ? */
|
||||
sz->per_rank += value & 0xff;
|
||||
sz->rows = value & 0xff;
|
||||
|
||||
value = spd_read_byte(device, SPD_COL_NUM); /* columns */
|
||||
if (value < 0) goto hw_err;
|
||||
if ((value & 0xff) == 0) goto val_err; //max is 11
|
||||
if ((value & 0xff) == 0) goto val_err; /* max is 11 */
|
||||
sz->per_rank += value & 0xff;
|
||||
sz->col = value & 0xff;
|
||||
|
||||
|
|
@ -740,9 +801,10 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
|
|||
sz->per_rank += log2(value) - 3; //64 bit So another 3 lines
|
||||
|
||||
/* How many ranks? */
|
||||
value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK); /* number of physical banks */
|
||||
/* number of physical banks */
|
||||
value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
|
||||
if (value < 0) goto hw_err;
|
||||
// value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT;
|
||||
/* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
|
||||
value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
|
||||
value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
|
||||
/*
|
||||
|
|
@ -785,11 +847,12 @@ hw_err:
|
|||
return;
|
||||
}
|
||||
|
||||
static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index, int is_Width128)
|
||||
|
||||
static void set_dimm_size(const struct mem_controller *ctrl,
|
||||
struct dimm_size *sz, unsigned index, int is_Width128)
|
||||
{
|
||||
uint32_t base0, base1;
|
||||
|
||||
|
||||
/* For each base register.
|
||||
* Place the dimm size in 32 MB quantities in the bits 31 - 21.
|
||||
* The initialize dimm size is in bits.
|
||||
|
|
@ -878,7 +941,9 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size *s
|
|||
11: 16 11 3 :8G
|
||||
*/
|
||||
|
||||
static void set_dimm_cs_map(const struct mem_controller *ctrl, struct dimm_size *sz, unsigned index)
|
||||
|
||||
static void set_dimm_cs_map(const struct mem_controller *ctrl,
|
||||
struct dimm_size *sz, unsigned index)
|
||||
{
|
||||
static const uint8_t cs_map_aaa[24] = {
|
||||
/* (bank=2, row=13, col=9)(3, 16, 11) ---> (0, 0, 0) (1, 3, 2) */
|
||||
|
|
@ -920,7 +985,9 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl, struct dimm_size
|
|||
|
||||
}
|
||||
|
||||
static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
|
||||
|
||||
static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask,
|
||||
struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -939,6 +1006,7 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask,
|
|||
return dimm_mask;
|
||||
}
|
||||
|
||||
|
||||
static void route_dram_accesses(const struct mem_controller *ctrl,
|
||||
unsigned long base_k, unsigned long limit_k)
|
||||
{
|
||||
|
|
@ -962,12 +1030,14 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
|
|||
|
||||
limit_reg = 0x44 + index;
|
||||
base_reg = 0x40 + index;
|
||||
for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device += PCI_DEV(0, 1, 0)) {
|
||||
for (device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1);
|
||||
device += PCI_DEV(0, 1, 0)) {
|
||||
pci_write_config32(device, limit_reg, limit);
|
||||
pci_write_config32(device, base_reg, base);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void set_top_mem(unsigned tom_k, unsigned hole_startk)
|
||||
{
|
||||
/* Error if I don't have memory */
|
||||
|
|
@ -1074,7 +1144,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
|
|||
* more than one and their is a power of two of them.
|
||||
*/
|
||||
bits = log2(chip_selects);
|
||||
if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { //chip_selects max = 8
|
||||
if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) {
|
||||
//chip_selects max = 8
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1147,6 +1218,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl)
|
|||
csbase = value;
|
||||
canidate = index;
|
||||
}
|
||||
|
||||
/* See if I have found a new canidate */
|
||||
if (csbase == 0) {
|
||||
break;
|
||||
|
|
@ -1200,19 +1272,24 @@ unsigned long memory_end_k(const struct mem_controller *ctrl, int max_node_id)
|
|||
return end_k;
|
||||
}
|
||||
|
||||
static void order_dimms(const struct mem_controller *ctrl, struct mem_info *meminfo)
|
||||
|
||||
static void order_dimms(const struct mem_controller *ctrl,
|
||||
struct mem_info *meminfo)
|
||||
{
|
||||
unsigned long tom_k, base_k;
|
||||
|
||||
if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
|
||||
if (read_option(CMOS_VSTART_interleave_chip_selects,
|
||||
CMOS_VLEN_interleave_chip_selects, 1) != 0) {
|
||||
tom_k = interleave_chip_selects(ctrl, meminfo->is_Width128);
|
||||
} else {
|
||||
print_debug("Interleaving disabled\r\n");
|
||||
tom_k = 0;
|
||||
}
|
||||
|
||||
if (!tom_k) {
|
||||
tom_k = order_chip_selects(ctrl);
|
||||
}
|
||||
|
||||
/* Compute the memory base address */
|
||||
base_k = memory_end_k(ctrl, ctrl->node_id);
|
||||
tom_k += base_k;
|
||||
|
|
@ -1220,7 +1297,9 @@ static void order_dimms(const struct mem_controller *ctrl, struct mem_info *memi
|
|||
set_top_mem(tom_k, 0);
|
||||
}
|
||||
|
||||
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask, struct mem_info *meminfo)
|
||||
|
||||
static long disable_dimm(const struct mem_controller *ctrl, unsigned index,
|
||||
long dimm_mask, struct mem_info *meminfo)
|
||||
{
|
||||
print_debug("disabling dimm");
|
||||
print_debug_hex8(index);
|
||||
|
|
@ -1238,7 +1317,9 @@ static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long
|
|||
return dimm_mask;
|
||||
}
|
||||
|
||||
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
|
||||
|
||||
static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
|
||||
long dimm_mask, struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
uint32_t registered;
|
||||
|
|
@ -1249,14 +1330,18 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
|
|||
if (!(dimm_mask & (1 << i))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
value = spd_read_byte(ctrl->channel0[i], SPD_DIMM_TYPE);
|
||||
if (value < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Registered dimm ? */
|
||||
value &= 0x3f;
|
||||
if ((value == SPD_DIMM_TYPE_RDIMM) || (value == SPD_DIMM_TYPE_mRDIMM)) {
|
||||
//check SPD_MOD_ATTRIB to verify it is SPD_MOD_ATTRIB_REGADC (0x11)?
|
||||
if ((value == SPD_DIMM_TYPE_RDIMM) ||
|
||||
(value == SPD_DIMM_TYPE_mRDIMM)) {
|
||||
/* check SPD_MOD_ATTRIB to verify it is
|
||||
SPD_MOD_ATTRIB_REGADC (0x11)? */
|
||||
registered |= (1<<i);
|
||||
}
|
||||
}
|
||||
|
|
@ -1294,6 +1379,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, long
|
|||
return dimm_mask;
|
||||
}
|
||||
|
||||
|
||||
static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
|
||||
{
|
||||
unsigned dimm_mask;
|
||||
|
|
@ -1320,6 +1406,7 @@ static unsigned int spd_detect_dimms(const struct mem_controller *ctrl)
|
|||
return dimm_mask;
|
||||
}
|
||||
|
||||
|
||||
static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_mask, struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -1356,7 +1443,8 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
|
|||
((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) {
|
||||
goto single_channel;
|
||||
}
|
||||
/* If the cpu is not capable of doing dual channels don't do dual channels */
|
||||
/* If the cpu is not capable of doing dual channels
|
||||
don't do dual channels */
|
||||
nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
|
||||
if (!(nbcap & NBCAP_128Bit)) {
|
||||
goto single_channel;
|
||||
|
|
@ -1523,11 +1611,13 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
|
|||
|
||||
}
|
||||
|
||||
|
||||
struct spd_set_memclk_result {
|
||||
const struct mem_param *param;
|
||||
long dimm_mask;
|
||||
};
|
||||
|
||||
|
||||
static unsigned convert_to_linear(unsigned value)
|
||||
{
|
||||
static const unsigned fraction[] = { 0x25, 0x33, 0x66, 0x75 };
|
||||
|
|
@ -1614,6 +1704,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
|
|||
if (value < 0) {
|
||||
goto hw_error;
|
||||
}
|
||||
|
||||
print_tx("\tindex:", index);
|
||||
print_tx("\t\tlatency:", latency);
|
||||
print_tx("\t\tvalue1:", value);
|
||||
|
|
@ -1637,13 +1728,16 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
|
|||
print_tx("\t\tnew_latency:", new_latency);
|
||||
|
||||
}
|
||||
|
||||
if (new_latency > 6){
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Does min_latency need to be increased? */
|
||||
if (new_cycle_time > min_cycle_time) {
|
||||
min_cycle_time = new_cycle_time;
|
||||
}
|
||||
|
||||
/* Does min_cycle_time need to be increased? */
|
||||
if (new_latency > min_latency) {
|
||||
min_latency = new_latency;
|
||||
|
|
@ -1667,6 +1761,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
|
|||
if (!(dimm_mask & (1 << i))) {
|
||||
continue;
|
||||
}
|
||||
|
||||
latencies = spd_read_byte(ctrl->channel0[i], SPD_CAS_LAT);
|
||||
if (latencies < 0) goto hw_error;
|
||||
if (latencies == 0) {
|
||||
|
|
@ -1820,9 +1915,11 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
|
|||
if (clocks < TT_MIN) {
|
||||
clocks = TT_MIN;
|
||||
}
|
||||
|
||||
if (clocks > TT_MAX) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
dtl = pci_read_config32(ctrl->f2, TT_REG);
|
||||
|
||||
old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
|
||||
|
|
@ -1836,16 +1933,20 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
|
||||
static int update_dimm_Trcd(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, int i)
|
||||
{
|
||||
return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRCD, DTL_TRCD_SHIFT, DTL_TRCD_MASK, DTL_TRCD_BASE, DTL_TRCD_MIN, DTL_TRCD_MAX);
|
||||
}
|
||||
|
||||
|
||||
static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
{
|
||||
return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRRD, DTL_TRRD_SHIFT, DTL_TRRD_MASK, DTL_TRRD_BASE, DTL_TRRD_MIN, DTL_TRRD_MAX);
|
||||
}
|
||||
|
||||
|
||||
static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
{
|
||||
unsigned clocks, old_clocks;
|
||||
|
|
@ -1866,28 +1967,34 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_
|
|||
if (clocks < DTL_TRAS_MIN) {
|
||||
clocks = DTL_TRAS_MIN;
|
||||
}
|
||||
|
||||
if (clocks > DTL_TRAS_MAX) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
|
||||
old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
|
||||
if (old_clocks >= clocks) { // someone did it?
|
||||
return 1;
|
||||
}
|
||||
|
||||
dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
|
||||
dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
|
||||
pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
static int update_dimm_Trp(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, int i)
|
||||
{
|
||||
return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_LOW, SPD_TRP, DTL_TRP_SHIFT, DTL_TRP_MASK, DTL_TRP_BASE, DTL_TRP_MIN, DTL_TRP_MAX);
|
||||
}
|
||||
|
||||
static int update_dimm_Trtp(const struct mem_controller *ctrl, const struct mem_param *param, int i, struct mem_info *meminfo)
|
||||
|
||||
static int update_dimm_Trtp(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, int i, struct mem_info *meminfo)
|
||||
{
|
||||
//need to figure if it is 32 byte burst or 64 bytes burst
|
||||
/* need to figure if it is 32 byte burst or 64 bytes burst */
|
||||
int offset = 2;
|
||||
if (!meminfo->is_Width128) {
|
||||
uint32_t dword;
|
||||
|
|
@ -1904,7 +2011,8 @@ static int update_dimm_Twr(const struct mem_controller *ctrl, const struct mem_p
|
|||
}
|
||||
|
||||
|
||||
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
static int update_dimm_Tref(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, int i)
|
||||
{
|
||||
uint32_t dth, dth_old;
|
||||
int value;
|
||||
|
|
@ -1928,7 +2036,9 @@ static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
|
||||
|
||||
static void set_4RankRDimm(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, struct mem_info *meminfo)
|
||||
{
|
||||
#if QRANK_DIMM_SUPPRT == 1
|
||||
int value;
|
||||
|
|
@ -1960,7 +2070,8 @@ static void set_4RankRDimm(const struct mem_controller *ctrl, const struct mem_p
|
|||
}
|
||||
|
||||
|
||||
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct mem_info *meminfo)
|
||||
static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
|
||||
struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -1982,7 +2093,6 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl, struct me
|
|||
mask_page_1k = 0;
|
||||
|
||||
for (i = 0; i < DIMM_SOCKETS; i++) {
|
||||
|
||||
if (!(dimm_mask & (1 << i))) {
|
||||
continue;
|
||||
}
|
||||
|
|
@ -2040,6 +2150,7 @@ static void set_dimm_x4(const struct mem_controller *ctrl, const struct mem_para
|
|||
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
|
||||
}
|
||||
|
||||
|
||||
static int count_ones(uint32_t dimm_mask)
|
||||
{
|
||||
int dimms;
|
||||
|
|
@ -2054,7 +2165,8 @@ static int count_ones(uint32_t dimm_mask)
|
|||
}
|
||||
|
||||
|
||||
static void set_DramTerm(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
|
||||
static void set_DramTerm(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, struct mem_info *meminfo)
|
||||
{
|
||||
uint32_t dcl;
|
||||
unsigned odt;
|
||||
|
|
@ -2081,7 +2193,8 @@ static void set_DramTerm(const struct mem_controller *ctrl, const struct mem_par
|
|||
}
|
||||
|
||||
|
||||
static void set_ecc(const struct mem_controller *ctrl,const struct mem_param *param, long dimm_mask, struct mem_info *meminfo)
|
||||
static void set_ecc(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, long dimm_mask, struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
int value;
|
||||
|
|
@ -2122,15 +2235,19 @@ static void set_ecc(const struct mem_controller *ctrl,const struct mem_param *pa
|
|||
}
|
||||
}
|
||||
|
||||
static int update_dimm_Twtr(const struct mem_controller *ctrl, const struct mem_param *param, int i)
|
||||
|
||||
static int update_dimm_Twtr(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, int i)
|
||||
{
|
||||
|
||||
return update_dimm_TT_1_4(ctrl, param, i, DRAM_TIMING_HIGH, SPD_TWTR, DTH_TWTR_SHIFT, DTH_TWTR_MASK, DTH_TWTR_BASE, DTH_TWTR_MIN, DTH_TWTR_MAX);
|
||||
|
||||
}
|
||||
|
||||
static void set_TT(const struct mem_controller *ctrl, const struct mem_param *param, unsigned TT_REG,
|
||||
unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX, unsigned val, const char *str)
|
||||
|
||||
static void set_TT(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, unsigned TT_REG, unsigned TT_SHIFT,
|
||||
unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX,
|
||||
unsigned val, const char *str)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
|
|
@ -2146,31 +2263,38 @@ static void set_TT(const struct mem_controller *ctrl, const struct mem_param *pa
|
|||
return;
|
||||
}
|
||||
|
||||
static void set_TrwtTO(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
|
||||
static void set_TrwtTO(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRWTTO_SHIFT, DTH_TRWTTO_MASK,DTH_TRWTTO_BASE, DTH_TRWTTO_MIN, DTH_TRWTTO_MAX, param->TrwtTO, "TrwtTO");
|
||||
}
|
||||
|
||||
|
||||
static void set_Twrrd(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRRD_SHIFT, DTH_TWRRD_MASK,DTH_TWRRD_BASE, DTH_TWRRD_MIN, DTH_TWRRD_MAX, param->Twrrd, "Twrrd");
|
||||
}
|
||||
|
||||
|
||||
static void set_Twrwr(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TWRWR_SHIFT, DTH_TWRWR_MASK,DTH_TWRWR_BASE, DTH_TWRWR_MIN, DTH_TWRWR_MAX, param->Twrwr, "Twrwr");
|
||||
}
|
||||
|
||||
|
||||
static void set_Trdrd(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_TIMING_HIGH, DTH_TRDRD_SHIFT, DTH_TRDRD_MASK,DTH_TRDRD_BASE, DTH_TRDRD_MIN, DTH_TRDRD_MAX, param->Trdrd, "Trdrd");
|
||||
}
|
||||
|
||||
|
||||
static void set_DcqBypassMax(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_CONFIG_HIGH, DCH_DcqBypassMax_SHIFT, DCH_DcqBypassMax_MASK,DCH_DcqBypassMax_BASE, DCH_DcqBypassMax_MIN, DCH_DcqBypassMax_MAX, param->DcqByPassMax, "DcqBypassMax"); // value need to be in CMOS
|
||||
}
|
||||
|
||||
|
||||
static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
|
||||
{
|
||||
static const uint8_t faw_1k[] = {8, 10, 13, 14};
|
||||
|
|
@ -2183,8 +2307,7 @@ static void set_Tfaw(const struct mem_controller *ctrl, const struct mem_param *
|
|||
|
||||
if (meminfo->page_1k_mask != 0) { //1k page
|
||||
faw = faw_1k[memclkfreq_index];
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
faw = faw_2k[memclkfreq_index];
|
||||
}
|
||||
|
||||
|
|
@ -2210,6 +2333,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
|
|||
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
|
||||
}
|
||||
|
||||
|
||||
static void set_SlowAccessMode(const struct mem_controller *ctrl)
|
||||
{
|
||||
uint32_t dch;
|
||||
|
|
@ -2330,8 +2454,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
|
|||
dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
|
||||
}
|
||||
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
|
||||
dwordx = 0x002f2f00;
|
||||
} else {
|
||||
|
|
@ -2402,7 +2525,8 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
|
|||
}
|
||||
|
||||
|
||||
static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo)
|
||||
static void set_RDqsEn(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param, struct mem_info *meminfo)
|
||||
{
|
||||
#if CPU_SOCKET_TYPE==0x10
|
||||
//only need to set for reg and x8
|
||||
|
|
@ -2420,7 +2544,8 @@ static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param
|
|||
}
|
||||
|
||||
|
||||
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
static void set_idle_cycle_limit(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param)
|
||||
{
|
||||
uint32_t dcm;
|
||||
/* AMD says to Hardcode this */
|
||||
|
|
@ -2431,13 +2556,14 @@ static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct
|
|||
pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
|
||||
}
|
||||
|
||||
static void set_RdWrQByp(const struct mem_controller *ctrl, const struct mem_param *param)
|
||||
|
||||
static void set_RdWrQByp(const struct mem_controller *ctrl,
|
||||
const struct mem_param *param)
|
||||
{
|
||||
set_TT(ctrl, param, DRAM_CTRL_MISC, DCM_RdWrQByp_SHIFT, DCM_RdWrQByp_MASK,0, 0, 3, 2, "RdWrQByp");
|
||||
}
|
||||
|
||||
|
||||
|
||||
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask, struct mem_info *meminfo)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -2521,7 +2647,8 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct
|
|||
return dimm_mask;
|
||||
}
|
||||
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo)
|
||||
static void sdram_set_spd_registers(const struct mem_controller *ctrl,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
struct spd_set_memclk_result result;
|
||||
const struct mem_param *param;
|
||||
|
|
@ -2625,9 +2752,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
|
|||
for (j = 0; j < controllers; j++) {
|
||||
pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
hoist = /* hole start address */
|
||||
((hole_startk << 10) & 0xff000000) +
|
||||
/* hole address to memory controller address */
|
||||
|
|
@ -2649,7 +2774,8 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
|
|||
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
|
||||
|
||||
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
|
||||
//We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some
|
||||
/* We need to double check if the hole_startk is valid, if it is equal
|
||||
to basek, we need to decrease it some */
|
||||
uint32_t basek_pri;
|
||||
for (i=0; i<controllers; i++) {
|
||||
uint32_t base;
|
||||
|
|
@ -2660,13 +2786,15 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
|
|||
}
|
||||
base_k = (base & 0xffff0000) >> 2;
|
||||
if (base_k == hole_startk) {
|
||||
hole_startk -= (base_k - basek_pri)>>1; // decrease mem hole startk to make sure it is on middle of previous node
|
||||
/* decrease mem hole startk to make sure it is
|
||||
on middle of previous node */
|
||||
hole_startk -= (base_k - basek_pri) >> 1;
|
||||
break; //only one hole
|
||||
}
|
||||
basek_pri = base_k;
|
||||
}
|
||||
#endif
|
||||
//find node index that need do set hole
|
||||
/* find node index that need do set hole */
|
||||
for (i=0; i < controllers; i++) {
|
||||
uint32_t base, limit;
|
||||
unsigned base_k, limit_k;
|
||||
|
|
@ -2687,14 +2815,14 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
|
|||
}
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo)
|
||||
|
||||
static void sdram_enable(int controllers, const struct mem_controller *ctrl,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
||||
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
|
||||
unsigned cpu_f0_f1[8];
|
||||
/* FIXME: How about 32 node machine later? */
|
||||
|
|
@ -2716,13 +2844,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
continue;
|
||||
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
|
||||
|
||||
// if no memory installed, disabled the interface
|
||||
/* if no memory installed, disabled the interface */
|
||||
if (sysinfo->meminfo[i].dimm_mask==0x00){
|
||||
dch |= DCH_DisDramInterface;
|
||||
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
|
||||
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
dch |= DCH_MemClkFreqVal;
|
||||
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
|
||||
/* address timing and Output driver comp Control */
|
||||
|
|
@ -2788,7 +2915,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
|
||||
dcl |= DCL_InitDram;
|
||||
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
|
||||
|
||||
}
|
||||
|
||||
for (i = 0; i < controllers; i++) {
|
||||
|
|
@ -2840,12 +2966,12 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
}
|
||||
|
||||
#if HW_MEM_HOLE_SIZEK != 0
|
||||
// init hw mem hole here
|
||||
/* init hw mem hole here */
|
||||
/* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */
|
||||
set_hw_mem_hole(controllers, ctrl);
|
||||
#endif
|
||||
|
||||
//store tom to sysinfo, and it will be used by dqs_timing
|
||||
/* store tom to sysinfo, and it will be used by dqs_timing */
|
||||
{
|
||||
msr_t msr;
|
||||
//[1M, TOM)
|
||||
|
|
@ -2880,7 +3006,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
#else
|
||||
|
||||
#if MEM_TRAIN_SEQ == 2
|
||||
//need to enable mtrr, so dqs training could access the test address
|
||||
/* need to enable mtrr, so dqs training could access the test address */
|
||||
setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
|
||||
#endif
|
||||
|
||||
|
|
@ -2907,7 +3033,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, str
|
|||
#endif
|
||||
|
||||
}
|
||||
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
|
||||
|
||||
|
||||
static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
|
||||
const uint16_t *spd_addr)
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
|
|
|
|||
Loading…
Reference in New Issue