t132: Implement clock initialization api for functional units
This api provides a common interface to initialize various clock sources, dividers as well as enabling the clock for various functional units. BUG=chrome-os-partner:31251 BRANCH=None TEST=Compiles successfully for rush and boots till last known good point. Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3 Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211765 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8921 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Furquan Shaikh
Patrick Georgi
parent
6d7c9acc17
commit
c41dfb0626
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@ -8,6 +8,7 @@ bootblock-y += i2c.c
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bootblock-y += dma.c
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bootblock-y += monotonic_timer.c
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bootblock-y += padconfig.c
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bootblock-y += funitcfg.c
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bootblock-y += reset.c
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bootblock-y += ../tegra/gpio.c
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bootblock-y += ../tegra/i2c.c
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@ -31,6 +32,7 @@ romstage-y += i2c.c
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romstage-y += dma.c
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romstage-y += monotonic_timer.c
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romstage-y += padconfig.c
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romstage-y += funitcfg.c
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romstage-y += romstage.c
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romstage-y += power.c
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romstage-y += sdram.c
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@ -51,6 +53,7 @@ ramstage-y += i2c.c
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ramstage-y += dma.c
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ramstage-y += monotonic_timer.c
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ramstage-y += padconfig.c
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ramstage-y += funitcfg.c
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ramstage-y += reset.c
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ramstage-y += ../tegra/apbmisc.c
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ramstage-y += ../tegra/gpio.c
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@ -576,6 +576,14 @@ void clock_init(void)
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graphics_pll();
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}
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void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
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u32 *rst_dev_clr_reg)
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{
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writel(val, clk_enb_set_reg);
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udelay(IO_STABILIZATION_DELAY);
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writel(val, rst_dev_clr_reg);
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}
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void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
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{
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if (l)
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@ -0,0 +1,157 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <soc/addressmap.h>
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#include <soc/funitcfg.h>
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#include <soc/clock.h>
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#include <soc/padconfig.h>
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#include <string.h>
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struct clk_set_data {
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size_t clk_enb_set_offset;
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size_t rst_dev_clr_offset;
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};
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struct funit_cfg_data {
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const char *name;
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size_t clk_src_offset;
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uint8_t clk_data_index;
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uint32_t clk_enb_val;
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};
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enum {
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CLK_L_SET = 0,
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CLK_H_SET = 1,
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CLK_U_SET = 2,
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CLK_V_SET = 3,
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CLK_W_SET = 4,
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CLK_X_SET = 5,
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};
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#define CLK_SET_OFFSETS(x) \
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{ \
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offsetof(struct clk_rst_ctlr, clk_enb_##x##_set), \
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offsetof(struct clk_rst_ctlr, rst_dev_##x##_clr) \
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}
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static const struct clk_set_data clk_data_arr[] = {
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[CLK_L_SET] = CLK_SET_OFFSETS(l),
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[CLK_H_SET] = CLK_SET_OFFSETS(h),
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[CLK_U_SET] = CLK_SET_OFFSETS(u),
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[CLK_V_SET] = CLK_SET_OFFSETS(v),
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[CLK_W_SET] = CLK_SET_OFFSETS(w),
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[CLK_X_SET] = CLK_SET_OFFSETS(x),
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};
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static const struct funit_cfg_data funit_data[] = {
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[FUNIT_SBC1] = {"sbc1", offsetof(struct clk_rst_ctlr, clk_src_sbc1),
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CLK_H_SET,
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CLK_H_SBC1},
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[FUNIT_SBC4] = {"sbc4", offsetof(struct clk_rst_ctlr, clk_src_sbc4),
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CLK_U_SET,
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CLK_U_SBC4},
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[FUNIT_I2C3] = {"i2c3", offsetof(struct clk_rst_ctlr, clk_src_i2c3),
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CLK_U_SET,
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CLK_U_I2C3},
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[FUNIT_I2C5] = {"i2c5", offsetof(struct clk_rst_ctlr, clk_src_i2c5),
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CLK_H_SET,
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CLK_H_I2C5},
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[FUNIT_SDMMC3] = {"sdmmc3", offsetof(struct clk_rst_ctlr, clk_src_sdmmc3),
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CLK_U_SET,
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CLK_U_SDMMC3},
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[FUNIT_SDMMC4] = {"sdmmc4", offsetof(struct clk_rst_ctlr, clk_src_sdmmc4),
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CLK_L_SET,
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CLK_L_SDMMC4},
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};
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static inline uint32_t get_clk_src_freq(uint32_t clk_src)
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{
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uint32_t freq = 0;
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switch(clk_src) {
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case CLK_M:
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freq = TEGRA_CLK_M_KHZ;
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break;
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case PLLP:
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freq = TEGRA_PLLP_KHZ;
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break;
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default:
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printk(BIOS_SPEW, "%s ERROR: Unknown clk_src %d\n",
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__func__,clk_src);
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}
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return freq;
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}
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void soc_configure_funits(const struct funit_cfg * const entries, size_t num)
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{
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size_t i;
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const char *funit_i2c = "i2c";
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uint32_t clk_div;
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uint32_t clk_div_mask;
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for (i = 0; i < num; i++) {
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uint8_t *rst_base = (uint8_t*)clk_rst;
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const struct funit_cfg * const entry = &entries[i];
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const struct funit_cfg_data *funit;
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const struct clk_set_data *clk_data;
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uint32_t *clk_src_reg, *clk_enb_set_reg, *rst_dev_clr_reg;
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uint32_t clk_src_freq;
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if (entry->funit_index >= FUNIT_INDEX_MAX) {
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printk(BIOS_ERR, "Error: Index out of bounds\n");
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continue;
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}
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funit = &funit_data[entry->funit_index];
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clk_data = &clk_data_arr[funit->clk_data_index];
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clk_src_reg = (uint32_t*)(rst_base + funit->clk_src_offset);
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clk_enb_set_reg = (uint32_t*)(rst_base
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+ clk_data->clk_enb_set_offset);
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rst_dev_clr_reg = (uint32_t*)(rst_base
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+ clk_data->rst_dev_clr_offset);
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clk_src_freq = get_clk_src_freq(entry->clk_src_id);
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if (strncmp(funit->name,funit_i2c,strlen(funit_i2c)) == 0) {
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/* I2C funit */
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clk_div = get_i2c_clk_div(clk_src_freq,
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entry->clk_dev_freq_khz);
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clk_div_mask = CLK_DIV_MASK_I2C;
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} else {
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/* Non I2C */
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clk_div = get_clk_div(clk_src_freq,entry->clk_dev_freq_khz);
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clk_div_mask = CLK_DIV_MASK;
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}
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_clock_set_div(clk_src_reg,funit->name,clk_div,
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clk_div_mask,entry->clk_src_id);
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clock_grp_enable_clear_reset(funit->clk_enb_val,
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clk_enb_set_reg,
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rst_dev_clr_reg);
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soc_configure_pads(entry->pad_cfg,entry->pad_cfg_size);
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}
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}
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@ -236,9 +236,14 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
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src << CLK_SOURCE_SHIFT | div);
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}
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#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1)
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#define get_clk_div(src,freq) CLK_DIVIDER(src,freq)
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#define CLK_DIV_MASK 0xff
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#define CLK_DIV_MASK_I2C 0xffff
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#define clock_configure_irregular_source(device, src, freq, src_id) \
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_clock_set_div(&clk_rst->clk_src_##device, #device, \
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CLK_DIVIDER(TEGRA_##src##_KHZ, freq), 0xff, src_id)
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get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, src_id)
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/* Warning: Some devices just use different bits for the same sources for no
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* apparent reason. *Always* double-check the TRM before trusting this macro. */
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@ -254,8 +259,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
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*/
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#define clock_configure_i2c_scl_freq(device, src, freq) \
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_clock_set_div(&clk_rst->clk_src_##device, #device, \
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div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
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0xffff, src)
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get_i2c_clk_div(TEGRA_##src##_KHZ, freq), \
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CLK_DIV_MASK_I2C, src)
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enum clock_source { /* Careful: Not true for all sources, always check TRM! */
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PLLP = 0,
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@ -288,6 +293,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
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void clock_cpu0_config(void);
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void clock_halt_avp(void);
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void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
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void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
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void clock_reset_l(u32 l);
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void clock_reset_h(u32 h);
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void clock_reset_u(u32 u);
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@ -0,0 +1,63 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
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#define __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
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#include <stdint.h>
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#include <soc/nvidia/tegra132/pinmux.h>
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#include <soc/padconfig.h>
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#include <soc/clock.h>
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#define FUNIT_INDEX(_name) FUNIT_##_name
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enum {
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FUNIT_NONE = 0,
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FUNIT_INDEX(SBC1),
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FUNIT_INDEX(SBC4),
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FUNIT_INDEX(I2C3),
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FUNIT_INDEX(I2C5),
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FUNIT_INDEX(SDMMC3),
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FUNIT_INDEX(SDMMC4),
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FUNIT_INDEX_MAX,
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};
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struct funit_cfg {
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uint32_t funit_index;
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uint32_t clk_src_id;
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uint32_t clk_dev_freq_khz;
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struct pad_config const* pad_cfg;
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size_t pad_cfg_size;
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};
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#define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size) \
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{ \
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.funit_index = FUNIT_INDEX(_funit), \
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.clk_src_id = _clk_src, \
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.clk_dev_freq_khz = _clk_freq, \
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.pad_cfg = _cfg, \
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.pad_cfg_size = _cfg_size, \
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}
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/*
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* Configure the funits associated with entry according to the configuration.
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*/
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void soc_configure_funits(const struct funit_cfg * const entries, size_t num);
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#endif /* __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H */
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