soc/intel/broadwell: Use Lynx Point IOBP code
Change-Id: I89832dd6089e1961b4ffdb5661dc98b26a5cb0a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52515 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
parent
dfb29fd701
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c423ce2f7f
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@ -1,11 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _BROADWELL_IOBP_H_
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#define _BROADWELL_IOBP_H_
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u32 pch_iobp_read(u32 address);
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void pch_iobp_write(u32 address, u32 data);
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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void pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp);
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#endif
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@ -9,8 +9,8 @@ romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
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smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c
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ramstage-y += hda.c
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ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c
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ramstage-y += iobp.c
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romstage-y += iobp.c
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ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
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romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c
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ramstage-y += fadt.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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@ -9,12 +9,12 @@
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#include <device/mmio.h>
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#include <soc/adsp.h>
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#include <soc/device_nvs.h>
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#include <soc/iobp.h>
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#include <soc/device_nvs.h>
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#include <soc/pch.h>
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#include <soc/ramstage.h>
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#include <soc/rcba.h>
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#include <soc/intel/broadwell/pch/chip.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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static void adsp_init(struct device *dev)
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{
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@ -1,139 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <delay.h>
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#include <soc/iobp.h>
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#include <soc/rcba.h>
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#define IOBP_RETRY 1000
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static inline int iobp_poll(void)
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{
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unsigned int try;
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for (try = IOBP_RETRY; try > 0; try--) {
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u16 status = RCBA16(IOBPS);
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if ((status & IOBPS_READY) == 0)
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return 1;
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udelay(10);
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}
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printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
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return 0;
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}
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u32 pch_iobp_read(u32 address)
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{
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u16 status;
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if (!iobp_poll())
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return 0;
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/* Set the address */
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RCBA32(IOBPIRI) = address;
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/* READ OPCODE */
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status = RCBA16(IOBPS);
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status &= ~IOBPS_MASK;
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status |= IOBPS_READ;
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RCBA16(IOBPS) = status;
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/* Undocumented magic */
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RCBA16(IOBPU) = IOBPU_MAGIC;
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/* Set ready bit */
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status = RCBA16(IOBPS);
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status |= IOBPS_READY;
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RCBA16(IOBPS) = status;
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if (!iobp_poll())
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return 0;
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/* Check for successful transaction */
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status = RCBA16(IOBPS);
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if (status & IOBPS_TX_MASK) {
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printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
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return 0;
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}
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/* Read IOBP data */
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return RCBA32(IOBPD);
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}
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void pch_iobp_write(u32 address, u32 data)
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{
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u16 status;
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if (!iobp_poll())
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return;
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/* Set the address */
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RCBA32(IOBPIRI) = address;
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/* WRITE OPCODE */
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status = RCBA16(IOBPS);
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status &= ~IOBPS_MASK;
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status |= IOBPS_WRITE;
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RCBA16(IOBPS) = status;
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RCBA32(IOBPD) = data;
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/* Undocumented magic */
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RCBA16(IOBPU) = IOBPU_MAGIC;
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/* Set ready bit */
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status = RCBA16(IOBPS);
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status |= IOBPS_READY;
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RCBA16(IOBPS) = status;
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if (!iobp_poll())
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return;
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/* Check for successful transaction */
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status = RCBA16(IOBPS);
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if (status & IOBPS_TX_MASK) {
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printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
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return;
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}
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printk(BIOS_SPEW, "IOBP: set 0x%08x to 0x%08x\n", address, data);
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}
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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{
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u32 data = pch_iobp_read(address);
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/* Update the data */
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data &= andvalue;
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data |= orvalue;
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pch_iobp_write(address, data);
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}
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void pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
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{
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if (!data || !resp)
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return;
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*resp = -1;
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if (!iobp_poll())
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return;
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/* RCBA2330[31:0] = Address */
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RCBA32(IOBPIRI) = addr;
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/* RCBA2338[15:8] = opcode */
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RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x00ff) | op_code;
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/* RCBA233A[15:8] = 0xf0 RCBA233A[7:0] = Route ID */
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RCBA16(IOBPU) = IOBPU_MAGIC | route_id;
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if (op_code == IOBP_PCICFG_WRITE)
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RCBA32(IOBPD) = *data;
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/* Set RCBA2338[0] to trigger IOBP transaction*/
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RCBA16(IOBPS) = RCBA16(IOBPS) | 0x1;
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if (!iobp_poll())
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return;
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*resp = (RCBA16(IOBPS) & IOBPS_TX_MASK) >> 1;
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*data = RCBA32(IOBPD);
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}
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@ -11,7 +11,6 @@
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#include <arch/ioapic.h>
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#include <acpi/acpi.h>
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#include <cpu/x86/smm.h>
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#include <soc/iobp.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/pch.h>
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@ -22,6 +21,7 @@
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#include <soc/intel/broadwell/pch/chip.h>
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#include <acpi/acpigen.h>
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#include <southbridge/intel/common/rtc.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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static void pch_enable_ioapic(struct device *dev)
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@ -5,13 +5,13 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <soc/iobp.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/rcba.h>
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#include <soc/serialio.h>
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#include <soc/spi.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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u8 pch_revision(void)
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{
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@ -9,11 +9,11 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <soc/lpc.h>
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#include <soc/iobp.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/rcba.h>
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#include <soc/intel/broadwell/pch/chip.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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#include <southbridge/intel/lynxpoint/lp_gpio.h>
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#include <delay.h>
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@ -7,11 +7,11 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <delay.h>
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#include <soc/iobp.h>
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#include <soc/ramstage.h>
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#include <soc/rcba.h>
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#include <soc/sata.h>
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#include <soc/intel/broadwell/pch/chip.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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static inline u32 sir_read(struct device *dev, int idx)
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{
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@ -7,7 +7,6 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/iobp.h>
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#include <soc/device_nvs.h>
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#include <soc/pci_devs.h>
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#include <soc/pch.h>
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@ -15,6 +14,7 @@
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#include <soc/rcba.h>
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#include <soc/serialio.h>
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#include <soc/intel/broadwell/pch/chip.h>
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#include <southbridge/intel/lynxpoint/iobp.h>
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/* Set D3Hot Power State in ACPI mode */
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static void serialio_enable_d3hot(struct resource *res)
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