cpu/amd/mtrr: Remove topmem global variables

The comments are not correct anymore. With AGESA there is no need to
synchronize TOM_MEMx msr's between AP's. It's also not the best place
to do so anyway.

Change-Id: Iecbe1553035680b7c3780338070b852606d74d15
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans 2021-10-28 12:35:39 +02:00 committed by Felix Held
parent b0db82dd24
commit c435038c55
8 changed files with 16 additions and 82 deletions

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@ -3,54 +3,11 @@
#include <amdblocks/biosram.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/cpu.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/cache.h>
/* These will likely move to some device node or cbmem. */
static uint64_t amd_topmem = 0;
static uint64_t amd_topmem2 = 0;
uint64_t bsp_topmem(void)
{
return amd_topmem;
}
uint64_t bsp_topmem2(void)
{
return amd_topmem2;
}
/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers,
* so they can be distributed to AP CPUs. Not strictly MTRRs,
* but this is not that bad a place to have this code.
*/
void setup_bsp_ramtop(void)
{
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
msr = rdmsr(TOP_MEM);
printk(BIOS_INFO,
"%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr.lo, msr.hi);
/* TOP_MEM2: the top of DRAM above 4G */
msr2 = rdmsr(TOP_MEM2);
printk(BIOS_INFO,
"%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;
amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;
}
void add_uma_resource_below_tolm(struct device *nb, int idx)
{
uint32_t topmem = bsp_topmem();
uint32_t topmem = amd_topmem();
uint32_t top_of_cacheable = restore_top_of_low_cacheable();
if (top_of_cacheable == topmem)

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@ -66,10 +66,16 @@ static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
);
}
/* To distribute topmem MSRs to APs. */
void setup_bsp_ramtop(void);
uint64_t bsp_topmem(void);
uint64_t bsp_topmem2(void);
static inline uint64_t amd_topmem(void)
{
return rdmsr(TOP_MEM).lo;
}
static inline uint64_t amd_topmem2(void)
{
msr_t msr = rdmsr(TOP_MEM2);
return (uint64_t)msr.hi << 32 | msr.lo;
}
#endif
#endif /* CPU_AMD_MTRR_H */

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@ -818,13 +818,6 @@ static struct device_operations cpu_bus_ops = {
static void root_complex_enable_dev(struct device *dev)
{
static int done = 0;
if (!done) {
setup_bsp_ramtop();
done = 1;
}
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;

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@ -737,7 +737,7 @@ static void domain_set_resources(struct device *dev)
sizek = 0;
}
else {
uint64_t topmem2 = bsp_topmem2();
uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@ -900,13 +900,6 @@ static struct device_operations cpu_bus_ops = {
static void root_complex_enable_dev(struct device *dev)
{
static int done = 0;
if (!done) {
setup_bsp_ramtop();
done = 1;
}
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;

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@ -750,7 +750,7 @@ static void domain_set_resources(struct device *dev)
sizek = 0;
}
else {
uint64_t topmem2 = bsp_topmem2();
uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@ -922,13 +922,6 @@ static struct device_operations cpu_bus_ops = {
static void root_complex_enable_dev(struct device *dev)
{
static int done = 0;
if (!done) {
setup_bsp_ramtop();
done = 1;
}
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;

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@ -770,7 +770,7 @@ static void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
/* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */
mmio_basek = bsp_topmem() >> 10;
mmio_basek = amd_topmem() >> 10;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare
@ -826,7 +826,7 @@ static void domain_read_resources(struct device *dev)
sizek = 0;
}
else {
uint64_t topmem2 = bsp_topmem2();
uint64_t topmem2 = amd_topmem2();
basek = 4*1024*1024;
sizek = topmem2/1024 - basek;
}
@ -995,13 +995,6 @@ static struct device_operations cpu_bus_ops = {
static void root_complex_enable_dev(struct device *dev)
{
static int done = 0;
if (!done) {
setup_bsp_ramtop();
done = 1;
}
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;

View File

@ -131,7 +131,6 @@ static void enable_dev(struct device *dev)
static void soc_init(void *chip_info)
{
fch_init(chip_info);
setup_bsp_ramtop();
}
static void soc_final(void *chip_info)

View File

@ -332,7 +332,7 @@ static const struct pci_driver family15_northbridge __pci_driver = {
*/
void amd_initcpuio(void)
{
uintptr_t topmem = bsp_topmem();
uintptr_t topmem = amd_topmem();
uintptr_t base, limit;
/* Enable legacy video routing: D18F1xF4 VGA Enable */