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qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32 

According to my SC7180 reference manual, these three GPIOs are in the
NORTH TLMM, but our pin table lists them as SOUTH. That means all
accesses our code has been doing to them have just been hitting empty
address space.

BUG=b:160115694

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If9c03ac890a7975855394c2e08b8433472df204d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Julius Werner 2020-07-27 17:07:30 -07:00 committed by Patrick Georgi
parent 683ac6f204
commit c435d3daa7
1 changed files with 3 additions and 3 deletions
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6
src/soc/qualcomm/sc7180/include/soc/gpio.h
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@ -159,10 +159,10 @@ enum {
RES_7),
PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6,
RES_7),
PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),