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cpu/intel/car/core2/cache_as_ram: Add x86_64 support 

Tested on Lenovo T500 with additional patches.

Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2020-09-28 22:31:06 +02:00 committed by Patrick Georgi
parent 6edaa21698
commit c439e07936
2 changed files with 21 additions and 5 deletions
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3
src/cpu/intel/car/cache_as_ram_symbols.inc
View File

@ -16,6 +16,9 @@ rom_mtrr_base:
car_mtrr_mask: car_mtrr_mask:
.uintptr_t _car_mtrr_mask .uintptr_t _car_mtrr_mask
car_mtrr_size:
.uintptr_t _car_mtrr_size
car_mtrr_start: car_mtrr_start:
.uintptr_t _car_mtrr_start .uintptr_t _car_mtrr_start

23
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -7,6 +7,8 @@
.section .init .section .init
.global bootblock_pre_c_entry .global bootblock_pre_c_entry
#include <cpu/intel/car/cache_as_ram_symbols.inc>
.code32 .code32
_cache_as_ram_setup: _cache_as_ram_setup:
@ -92,7 +94,7 @@ addrsize_set_high:
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr rdmsr
movl $_car_mtrr_mask, %eax movl car_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
@ -119,8 +121,8 @@ addrsize_set_high:
/* Clear the cache memory region. This will also fill up the cache. */ /* Clear the cache memory region. This will also fill up the cache. */
cld cld
xorl %eax, %eax xorl %eax, %eax
movl $_car_mtrr_start, %edi movl car_mtrr_start, %edi
movl $_car_mtrr_size, %ecx movl car_mtrr_size, %ecx
shr $2, %ecx shr $2, %ecx
rep stosl rep stosl
@ -134,12 +136,12 @@ addrsize_set_high:
movl $MTRR_PHYS_BASE(1), %ecx movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx xorl %edx, %edx
movl $_program, %eax movl $_program, %eax
andl $_xip_mtrr_mask, %eax andl xip_mtrr_mask, %eax
orl $MTRR_TYPE_WRPROT, %eax orl $MTRR_TYPE_WRPROT, %eax
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
rdmsr rdmsr
movl $_xip_mtrr_mask, %eax movl xip_mtrr_mask, %eax
orl $MTRR_PHYS_MASK_VALID, %eax orl $MTRR_PHYS_MASK_VALID, %eax
wrmsr wrmsr
@ -157,6 +159,16 @@ addrsize_set_high:
andl $0xfffffff0, %esp andl $0xfffffff0, %esp
subl $4, %esp subl $4, %esp
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
movd %mm2, %rdi
shlq $32, %rdi
movd %mm1, %rsi
or %rsi, %rdi
movd %mm0, %rsi
#else
/* push TSC and BIST to stack */ /* push TSC and BIST to stack */
movd %mm0, %eax movd %mm0, %eax
pushl %eax /* BIST */ pushl %eax /* BIST */
@ -164,6 +176,7 @@ addrsize_set_high:
pushl %eax /* tsc[63:32] */ pushl %eax /* tsc[63:32] */
movd %mm1, %eax movd %mm1, %eax
pushl %eax /* tsc[31:0] */ pushl %eax /* tsc[31:0] */
#endif
before_c_entry: before_c_entry:
post_code(0x29) post_code(0x29)