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asus/f2a85-m: Switch away from AGESA_LEGACY 

Change-Id: I7ba328c73f5fb44e50f00cb93db4f7ac8afbfdc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18712
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2016-12-20 06:43:45 +02:00
parent bf2d2fe557
commit c43d5049ea
2 changed files with 32 additions and 92 deletions
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1
src/mainboard/asus/f2a85-m/Kconfig
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@ -18,7 +18,6 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
config BOARD_SPECIFIC_OPTIONS # dummy config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY15_TN select CPU_AMD_AGESA_FAMILY15_TN
select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
select SOUTHBRIDGE_AMD_AGESA_HUDSON select SOUTHBRIDGE_AMD_AGESA_HUDSON

123
src/mainboard/asus/f2a85-m/romstage.c
View File

@ -14,22 +14,10 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/stages.h>
#include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/car.h> #include <northbridge/amd/agesa/state_machine.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pnp_def.h>
#include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/common/amd_defs.h>
#include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/hudson.h>
#include <southbridge/amd/agesa/hudson/smbus.h> #include <southbridge/amd/agesa/hudson/smbus.h>
@ -76,98 +64,51 @@ static void superio_init_m_pro(void)
nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE); nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
} }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void board_BeforeAgesa(struct sysinfo *cb)
{ {
u32 val;
u8 byte; u8 byte;
pci_devfn_t dev; pci_devfn_t dev;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
hudson_pci_port80(); hudson_pci_port80();
else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
hudson_lpc_port80(); hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */
dev = PCI_DEV(0, 0x14, 3);
byte = pci_read_config8(dev, 0x48);
byte |= 3; /* 2e, 2f */
pci_write_config8(dev, 0x48, byte);
/* enable SIO LPC decode */ /* enable serial decode */
dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x44);
byte = pci_read_config8(dev, 0x48); byte |= (1 << 6); /* 0x3f8 */
byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x44, byte);
pci_write_config8(dev, 0x48, byte);
/* enable serial decode */ post_code(0x30);
byte = pci_read_config8(dev, 0x44);
byte |= (1 << 6); /* 0x3f8 */
pci_write_config8(dev, 0x44, byte);
post_code(0x30); /* enable SB MMIO space */
outb(0x24, 0xcd6);
outb(0x1, 0xcd7);
/* enable SB MMIO space */ /* enable SIO clock */
outb(0x24, 0xcd6); sbxxx_enable_48mhzout();
outb(0x1, 0xcd7);
/* enable SIO clock */ if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
sbxxx_enable_48mhzout(); superio_init_m_pro();
else
superio_init_m();
if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)) /* turn on secondary smbus at b20 */
superio_init_m_pro(); outb(0x28, 0xcd6);
else byte = inb(0xcd7);
superio_init_m(); byte |= 1;
outb(byte, 0xcd7);
console_init(); /* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
/* turn on secondary smbus at b20 */ /* default is byte = 0x0, so no need to set it in this case */
outb(0x28, 0xcd6); if (byte)
byte = inb(0xcd7); do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
byte |= 1;
outb(byte, 0xcd7);
/* set DDR3 voltage */
byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
/* default is byte = 0x0, so no need to set it in this case */
if (byte)
do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
amd_initcpuio();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
} }