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veyron: Sync up SDRAM configurations 

This patch adds all SDRAM configurations currently in use for any Veyron
board to all boards. In the future we might decide that we want to reuse
known good memory from one board on another, and having all of these in
there already might help us avoid a firmware rev. We can still
differentiate them later if the need ever arises.

Not touching Rialto since it already decided to go its own way and
replace an existing RAM code with it's own 1GB configuration. Also
adjusting the names of the recently added DDR3 4GB configs to fit the
existing scheme.

Includes changes from "veyron: The ODT function is disabled LPDDR3".

BRANCH=veyron
BUG=None
TEST=Compiled all Veyron boards, booted on Jerry.

Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284
Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255665
Reviewed-on: http://review.coreboot.org/9829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner 2015-02-18 18:00:07 -08:00 committed by Patrick Georgi
parent 5c8aacfa3d
commit c447f43f94
38 changed files with 2367 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/mainboard/google/veyron_brain/sdram_configs.c
View File

@ -26,21 +26,21 @@
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

78
src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-2GB.inc Normal file
View File

@ -0,0 +1,78 @@
{
/* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

1
src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc → src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-hynix-4GB.inc
View File

@ -1,4 +1,5 @@
{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,

1
src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc → src/mainboard/google/veyron_brain/sdram_inf/sdram-ddr3-samsung-4GB.inc
View File

@ -1,4 +1,5 @@
{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,

78
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc Normal file
View File

@ -0,0 +1,78 @@
{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

77
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-4GB.inc Normal file
View File

@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

77
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB.inc Normal file
View File

@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

14
src/mainboard/google/veyron_danger/sdram_configs.c
View File

@ -26,21 +26,21 @@
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

151
src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-2GB.inc
View File

@ -1,77 +1,78 @@
{
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x35,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xBB,
.trp = 0x8,
.trtw = 0x4,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x6,
.tras = 0x14,
.trc = 0x1D,
.trcd = 0x8,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x200,
.txp = 0x4,
.txpdll = 0xD,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x6,
.tcksrx = 0x6,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x36,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x3AD48890,
.dtpr1 = 0xBB08D8,
.dtpr2 = 0x1002B600,
.mr[0] = 0x840,
.mr[1] = 0x40,
.mr[2] = 0x8,
.mr[3] = 0x0
},
.noc_timing = 0x2891E41D,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
/* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-hynix-4GB.inc Normal file
View File

@ -0,0 +1,78 @@
{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_danger/sdram_inf/sdram-ddr3-samsung-4GB.inc Normal file
View File

@ -0,0 +1,78 @@
{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 4,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

77
src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

77
src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

10
src/mainboard/google/veyron_jerry/sdram_configs.c
View File

@ -26,21 +26,21 @@
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-K4B8G1646Q-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-H5TC8G63XXX-4GB.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

78
src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_jerry/sdram_inf/sdram-ddr3-samsung-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 4,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

77
src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

77
src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-samsung-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

14
src/mainboard/google/veyron_mighty/sdram_configs.c
View File

@ -26,21 +26,21 @@
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

78
src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-hynix-2GB.inc Normal file
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{
/* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
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{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_mighty/sdram_inf/sdram-ddr3-samsung-4GB.inc Normal file
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{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 4,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-hynix-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

77
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{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

77
src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-samsung-4GB.inc Normal file
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{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

14
src/mainboard/google/veyron_pinky/sdram_configs.c
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@ -26,21 +26,21 @@
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

78
src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-2GB.inc Normal file
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{
/* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
src/mainboard/google/veyron_pinky/sdram_inf/sdram-ddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
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@ -0,0 +1,78 @@
{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 4,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

77
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

77
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-samsung-4GB.inc Normal file
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@ -0,0 +1,77 @@
{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

8
src/mainboard/google/veyron_speedy/sdram_configs.c
View File

@ -30,8 +30,8 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
@ -39,8 +39,8 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1111 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()

78
src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Hynic H5TC4G63CFR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-hynix-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
src/mainboard/google/veyron_speedy/sdram_inf/sdram-ddr3-samsung-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0x10,
.cs1_row = 0x10
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 4,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},