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Stoney Ridge Platforms: Make AGESA callout tables common 

There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.

Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd

Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.

Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4.  A bug has been filed for support for
the upcoming Grunt platform.

BUG=b:67209686
TEST=Build and boot on Kahlee

Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Martin Roth 2017-10-02 13:46:50 -06:00
parent 44aaf6137d
commit c450fbe909
8 changed files with 177 additions and 222 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
src/mainboard/amd/gardenia/BiosCallOuts.c
View File

@ -27,7 +27,7 @@
* software switches the I2C address. AMD recommends using IMC
* to control fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
imc_reg_init();
@ -43,76 +43,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC));
}
static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
oem_fan_control(FchParams_env);
/* XHCI configuration */
if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
FchParams_env->Usb.Xhci0Enable = TRUE;
else
FchParams_env->Usb.Xhci0Enable = FALSE;
FchParams_env->Usb.Xhci1Enable = FALSE;
/* 8: If USB3 port is unremoveable. */
FchParams_env->Usb.USB30PortInit = 8;
/* SATA configuration */
FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
case SataLegacyIde:
FchParams_env->Sata.SataIdeMode = FALSE;
break;
case SataIde2Ahci:
case SataIde2Ahci7804:
default: /* SataNativeIde */
FchParams_env->Sata.SataIdeMode = TRUE;
break;
}
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
}
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
/* Required callouts */
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps },
{AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl },
{AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished },
{AGESA_IDLE_AN_AP, agesa_IdleAnAp },
/* Optional callouts */
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
//AgesaHeapRebase - Hook ID?
{AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported },
{AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage },
{AGESA_FCH_OEM_CALLOUT, fch_initenv },
{AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported },
{AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported },
/* Deprecated */
{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported},
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

23
src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
View File

@ -45,26 +45,7 @@ static const GPIO_CONTROL oem_gardenia_gpio[] = {
{-1}
};
static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.SataEnable = sb_sata_enable();
FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
}
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{AGESA_FCH_OEM_CALLOUT, fch_initreset },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

77
src/mainboard/google/kahlee/BiosCallOuts.c
View File

@ -21,79 +21,10 @@
extern const GPIO_CONTROL oem_kahlee_gpio[];
static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
/* XHCI configuration */
if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
FchParams_env->Usb.Xhci0Enable = TRUE;
else
FchParams_env->Usb.Xhci0Enable = FALSE;
FchParams_env->Usb.Xhci1Enable = FALSE;
/* 8: If USB3 port is unremoveable. */
FchParams_env->Usb.USB30PortInit = 8;
/* SATA configuration */
FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
case SataLegacyIde:
FchParams_env->Sata.SataIdeMode = FALSE;
break;
case SataIde2Ahci:
case SataIde2Ahci7804:
default: /* SataNativeIde */
FchParams_env->Sata.SataIdeMode = TRUE;
break;
}
/* SDHCI/MMC configuration */
FchParams_env->Sd.SdSlotType = 1; /* eMMC */
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
/* SDHCI/MMC configuration */
FchParams_env->Sd.SdSlotType = 1; // EMMC
}
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
/* Required callouts */
{AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{AGESA_DO_RESET, agesa_Reset },
{AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{AGESA_READ_SPD, agesa_ReadSpd },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps },
{AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl },
{AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished },
{AGESA_IDLE_AN_AP, agesa_IdleAnAp },
/* Optional callouts */
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
//AgesaHeapRebase - Hook ID?
{AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported },
{AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported },
{AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported },
{AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage },
{AGESA_FCH_OEM_CALLOUT, fch_initenv },
{AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported },
{AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported },
/* Deprecated */
{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported},
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

24
src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
View File

@ -21,27 +21,7 @@
extern const GPIO_CONTROL oem_kahlee_gpio[];
static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.SataEnable = sb_sata_enable();
FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
}
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{AGESA_DO_RESET, agesa_Reset },
{AGESA_FCH_OEM_CALLOUT, fch_initreset },
{AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }
};
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);

9
src/soc/amd/common/BiosCallOuts.h
View File

@ -19,6 +19,7 @@
#include <Porting.h>
#include <AGESA.h>
#include <FchPlatform.h>
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000
@ -48,8 +49,6 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData,
VOID *ConfigPrt);
AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data,
VOID *ConfigPtr);
AGESA_STATUS agesa_RunFcnOnAllAps(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_LateRunApTask(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_PcieSlotResetControl(UINT32 Func, UINTN Data,
@ -60,6 +59,12 @@ AGESA_STATUS agesa_IdleAnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr);
AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset);
void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env);
void oem_fan_control(FCH_DATA_BLOCK *FchParams);
typedef struct {
UINT32 CalloutName;
CALLOUT_ENTRY CalloutPtr;

75
src/soc/amd/common/def_callouts.c
View File

@ -15,16 +15,56 @@
*/
#include <cbfs.h>
#include <spd_bin.h>
#include <AGESA.h>
#include <amdlib.h>
#include <Ids.h>
#include <agesawrapper.h>
#include <BiosCallOuts.h>
#include <dimmSpd.h>
#include <soc/southbridge.h>
#if ENV_BOOTBLOCK
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
{ AGESA_DO_RESET, agesa_Reset },
{ AGESA_FCH_OEM_CALLOUT, agesa_fch_initreset },
{ AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }
};
#else
const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
/* Required callouts */
{ AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer },
{ AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer },
{ AGESA_DO_RESET, agesa_Reset },
{ AGESA_LOCATE_BUFFER, agesa_LocateBuffer },
{ AGESA_READ_SPD, agesa_ReadSpd },
{ AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{ AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps },
{ AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask },
{ AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl },
{ AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished },
{ AGESA_IDLE_AN_AP, agesa_IdleAnAp },
/* Optional callouts */
{ AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
//AgesaHeapRebase - Hook ID?
{ AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported },
{ AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported },
{ AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported },
{ AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported },
{ AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage },
{ AGESA_FCH_OEM_CALLOUT, agesa_fch_initenv },
{ AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported },
{ AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported },
/* Deprecated */
{ AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported},
{ AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
};
#endif
const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
UINTN i;
@ -115,37 +155,6 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData,
return pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING;
}
AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
Status = AmdMemoryReadSPD(Func, Data, ConfigPtr);
#endif
return Status;
}
AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId != 0)
return AGESA_UNSUPPORTED;
/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, 0) < 0)
die("No SPD data\n");
Status = AGESA_SUCCESS;
#endif
return Status;
}
AGESA_STATUS agesa_RunFcnOnAllAps(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
printk(BIOS_WARNING, "Warning - Missing AGESA callout: %s\n", __func__);

115
src/soc/amd/stoneyridge/BiosCallOuts.c Normal file
View File

@ -0,0 +1,115 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
* Copyright (C) 2017 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_def.h>
#include <BiosCallOuts.h>
#include <soc/southbridge.h>
#include <agesawrapper.h>
#include <AGESA.h>
#include <amdlib.h>
#include <dimmSpd.h>
AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset;
FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
FchParams_reset->FchReset.SataEnable = sb_sata_enable();
FchParams_reset->FchReset.IdeEnable = sb_ide_enable();
/* Get platform specific configuration changes */
platform_FchParams_reset(FchParams_reset);
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
}
AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM))
oem_fan_control(FchParams_env);
/* XHCI configuration */
if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE))
FchParams_env->Usb.Xhci0Enable = TRUE;
else
FchParams_env->Usb.Xhci0Enable = FALSE;
FchParams_env->Usb.Xhci1Enable = FALSE;
/* 8: If USB3 port is unremoveable. */
FchParams_env->Usb.USB30PortInit = 8;
/* SATA configuration */
FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) {
case SataRaid:
case SataAhci:
case SataAhci7804:
case SataLegacyIde:
FchParams_env->Sata.SataIdeMode = FALSE;
break;
case SataIde2Ahci:
case SataIde2Ahci7804:
default: /* SataNativeIde */
FchParams_env->Sata.SataIdeMode = TRUE;
break;
}
/* Platform updates */
platform_FchParams_env(FchParams_env);
printk(BIOS_DEBUG, "Done\n");
}
return AGESA_SUCCESS;
}
AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status = AGESA_UNSUPPORTED;
if (!ENV_ROMSTAGE)
return Status;
if (IS_ENABLED(CONFIG_GENERIC_SPD_BIN)) {
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
if (info->MemChannelId > 0)
return AGESA_UNSUPPORTED;
if (info->SocketId != 0)
return AGESA_UNSUPPORTED;
if (info->DimmId > 1)
return AGESA_UNSUPPORTED;
die("SPD in cbfs not yet supported.\n");
} else {
Status = AmdMemoryReadSPD(Func, Data, ConfigPtr);
}
return Status;
}

3
src/soc/amd/stoneyridge/Makefile.inc
View File

@ -38,12 +38,14 @@ subdirs-y += ../../../cpu/x86/pae
subdirs-y += ../../../cpu/x86/smm
bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
bootblock-y += BiosCallOuts.c
bootblock-y += fixme.c
bootblock-y += bootblock/bootblock.c
bootblock-y += early_setup.c
bootblock-y += pmutil.c
bootblock-y += tsc_freq.c
romstage-y += BiosCallOuts.c
romstage-y += romstage.c
romstage-y += early_setup.c
romstage-y += dimmSpd.c
@ -66,6 +68,7 @@ verstage-y += tsc_freq.c
postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
postcar-y += ramtop.c
ramstage-y += BiosCallOuts.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c