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mb/google/guybrush: Enable some PCIe power saving features 

Enable ASPM, Common Clock and Clock Power Managment. Accomplish this
by adding the options in the platform Kconfig as well as dxio
descriptors.

BUG=b:187743927
TEST=Boot to ChromeOS and see ASPM, CC and Clock PM enabled with lspci

Change-Id: Iefc4b5b489cb8caf59f21dd4333d7af66ba47c32
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54282
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt Papageorge 2021-05-13 15:59:57 -05:00 committed by Patrick Georgi
parent 76619b01c8
commit c46bb69495
2 changed files with 7 additions and 0 deletions
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3
src/mainboard/google/guybrush/Kconfig
View File

@ -32,6 +32,9 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_I2C_TPM_CR50
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select PCIEXP_ASPM
select PCIEXP_CLK_PM
select PCIEXP_COMMON_CLOCK
select PSP_DISABLE_POSTCODES select PSP_DISABLE_POSTCODES
select SOC_AMD_CEZANNE select SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_COMMON_BLOCK_USE_ESPI

4
src/mainboard/google/guybrush/port_descriptors.c
View File

@ -13,6 +13,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 0, .end_logical_lane = 0,
.device_number = 2, .device_number = 2,
.function_number = 1, .function_number = 1,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ0, .clk_req = CLK_REQ0,
.gpio_group_id = GPIO_29, .gpio_group_id = GPIO_29,
@ -25,6 +26,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 1, .end_logical_lane = 1,
.device_number = 2, .device_number = 2,
.function_number = 2, .function_number = 2,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ1, .clk_req = CLK_REQ1,
.gpio_group_id = GPIO_70, .gpio_group_id = GPIO_70,
@ -37,6 +39,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 2, .end_logical_lane = 2,
.device_number = 2, .device_number = 2,
.function_number = 3, .function_number = 3,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ2, .clk_req = CLK_REQ2,
.gpio_group_id = GPIO_18, .gpio_group_id = GPIO_18,
@ -49,6 +52,7 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
.end_logical_lane = 7, .end_logical_lane = 7,
.device_number = 2, .device_number = 2,
.function_number = 4, .function_number = 4,
.link_aspm = ASPM_L1,
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ3, .clk_req = CLK_REQ3,
.gpio_group_id = GPIO_40, .gpio_group_id = GPIO_40,