soc/amd/common/block/spi: Add SPI config to Kconfig
Currently, The SPI speed/mode configuration is split between Kconfig and devicetree. We'd like to have everything in one place. Since we need the fast-read speed and the mode available in the Makefile to build the AMD EFS table, we currently need it in Kconfig. Move all of the settings to Kconfig and remove them from Devicetree in a later commit. BUG=b:195943311 TEST=boot majolica & guybrush, verify spi settings Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -17,6 +17,7 @@ config SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST
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config EFS_SPI_READ_MODE
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int
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range 0 7
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default 0 if EM100
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default 2
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help
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SPI read mode to be programmed by the PSP.
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@ -35,6 +36,7 @@ config EFS_SPI_READ_MODE
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config EFS_SPI_SPEED
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int
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range 0 5
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default 3 if EM100
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default 0
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help
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SPI Fast Speed to be programmed by the PSP.
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@ -56,3 +58,45 @@ config EFS_SPI_MICRON_FLAG
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0: Board does not use Micron parts
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1: Board always uses Micron parts
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2: Micron parts are optional
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config NORMAL_READ_SPI_SPEED
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int
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range 0 5
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default 3 if EM100
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default 1
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help
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SPI Normal Speed to be programmed by coreboot.
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0: 66.66Mhz
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1: 33.33MHz
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2: 22.22MHz
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3: 16.66MHz
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4: 100MHz
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5: 800KHz
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config ALT_SPI_SPEED
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int
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range 0 5
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default 3 if EM100
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default 0
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help
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SPI ALT Speed to be programmed by coreboot.
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0: 66.66Mhz
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1: 33.33MHz
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2: 22.22MHz
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3: 16.66MHz
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4: 100MHz
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5: 800KHz
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config TPM_SPI_SPEED
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int
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range 0 5
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default 3 if EM100
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default 0
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help
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SPI TPM Speed to be programmed by coreboot.
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0: 66.66Mhz
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1: 33.33MHz
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2: 22.22MHz
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3: 16.66MHz
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4: 100MHz
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5: 800KHz
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